root/WaveDev/trunk/WaveDev/wavedev/generate/templates/custom_ports/genStructure.py @ 4342

Revision 4342, 60.4 KB (checked in by jgaeddert, 6 years ago)

changing OWD-generated configure.ac file to improve automake utilities
  • Property svn:executable set to *
Line 
1#! /usr/bin/env python
2
3## Copyright 2005, 2006 Virginia Polytechnic Institute and State University
4##
5## This file is part of the OSSIE Waveform Developer.
6##
7## OSSIE Waveform Developer is free software; you can redistribute it and/or modify
8## it under the terms of the GNU General Public License as published by
9## the Free Software Foundation; either version 2 of the License, or
10## (at your option) any later version.
11##
12## OSSIE Waveform Developer is distributed in the hope that it will be useful,
13## but WITHOUT ANY WARRANTY; without even the implied warranty of
14## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15## GNU General Public License for more details.
16##
17## You should have received a copy of the GNU General Public License
18## along with OSSIE Waveform Developer; if not, write to the Free Software
19## Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20
21import sys, os, shutil
22from errorMsg import *
23
24class genAll:
25  def __init__(self,path,active_wave):
26    if path[len(path)-1] != '/':
27        path = path + '/'
28    self.path = path
29    self.active_wave = active_wave
30
31  ##############################################################################
32  ## genDirs - this function generates the directory structure for the generated
33  ##           code for the waveform; puts required files in main folder
34  ##############################################################################
35  def genDirs(self):
36    if os.path.exists(self.path) == False:
37       errorMsg(self,"Waveform already exists - exiting")
38       exit(1)
39       
40    if os.path.exists(self.path+self.active_wave.name) == False:   
41        os.mkdir(self.path + self.active_wave.name)
42     
43    #the aclocal.d stuff is commented out because the aclocal.d folder
44    #should no longer be necessary with updates to reconf and configure.ac
45    #see autofoo updates by ballister and gaedert   
46    #if os.path.exists(self.path+self.active_wave.name+'/aclocal.d') == False:   
47    #    os.mkdir(self.path + self.active_wave.name + '/aclocal.d')
48       
49    #for x in os.listdir('generate/aclocal.d/'):
50    #    if not os.path.isdir(x):
51    #        shutil.copy('generate/aclocal.d/' + x,self.path + self.active_wave.name + '/aclocal.d')
52   
53    shutil.copy('generate/reconf',self.path + self.active_wave.name)
54    #for x in os.listdir('generate/basic_xml/'):
55    #    if not os.path.isdir(x):
56    #        shutil.copy('generate/basic_xml/' + x,self.path + self.active_wave.name)
57   
58    for x in self.active_wave.components:
59        if x.generate:
60            if os.path.exists(self.path+x.name) == False:
61                os.mkdir(self.path+x.name)
62            if x.AssemblyController != True:
63                #if os.path.exists(self.path+x.name+'/aclocal.d') == False:   
64                #    os.mkdir(self.path + x.name + '/aclocal.d')
65                #for f in os.listdir('generate/aclocal.d/'):
66                #    if not os.path.isdir(f):
67                #        shutil.copy('generate/aclocal.d/' + f,self.path + x.name + '/aclocal.d')
68                shutil.copy('generate/reconf',self.path + x.name)
69                #for f in os.listdir('generate/basic_xml/'):
70                #    if not os.path.isdir(f):
71                #        shutil.copy('generate/basic_xml/' + f,self.path + x.name)
72                shutil.copy('generate/LICENSE',self.path + x.name)
73               
74  ##############################################################################
75  ## writeMakefiles - generates the make file for the waveform and then calls
76  ##                  writeCompMakefile for each seperate component
77  ##############################################################################
78  def writeMakefiles(self,DevMan_flag):
79    output = open(self.path + self.active_wave.name + '/Makefile.am','w')
80
81    Flags = ["-Wall"]
82    self.info2str(output,"AM_CXXFLAGS = ",Flags,1)
83   
84    tstr = "ossieName = " + self.active_wave.name + '\n\n'
85    output.write(tstr)
86   
87    tstr = "SUBDIRS = "
88    for c in self.active_wave.components:
89        if c.AssemblyController == True and c.generate:
90            tstr += c.name + '\n\n'
91            output.write(tstr)   
92   
93#    tstr = "waveformdir = $(prefix)/dom/waveforms/$(ossieName)\n"
94    tstr = "waveformdir = $(prefix)/dom/waveforms/\n"
95
96
97    output.write(tstr)
98
99    waveform_data = []
100    waveform_data.append(self.active_wave.name + ".sad.xml")
101    waveform_data.append(self.active_wave.name + "_DAS.xml")
102    # If there is only one node - then install device manager files as well
103    #if DevMan_flag:
104    #    waveform_data.append("DeviceManager.dcd.xml")
105    #    waveform_data.append("DeviceManager.spd.xml")
106    #    waveform_data.append("DeviceManager.scd.xml")
107    #    waveform_data.append("DeviceManager.prf.xml")
108    #waveform_data.append("DomainManager.dmd.xml")
109    #waveform_data.append("DomainManager.spd.xml")
110    #waveform_data.append("DomainManager.scd.xml")
111    #waveform_data.append("DomainManager.prf.xml")
112
113    self.info2str(output,"dist_waveform_DATA = ", waveform_data,1)
114
115    output.close()
116   
117    for c in self.active_wave.components:
118        if c.generate:
119            tmpPath = self.path + c.name
120            self.writeCompMakefile(c,tmpPath)
121           
122  ##############################################################################
123  ## writeCompMakefilee - generates the make file for an indivdual component
124  ##############################################################################
125  def writeCompMakefile(self,comp,compPath):
126    if compPath[len(compPath)-1] != '/':
127        compPath = compPath + '/'
128   
129    header = "%SK.cpp %.h : %.idl\n\t@IDL@ @IDL_FLAGS@ "
130    header += "-bcxx -Wbh=.h -Wbs=SK.cpp -Wbkeep_inc_path $<\n\n"
131    header += "%.idl :\n\tcp @SI_PATH@/standardinterfaces/$@ .\n"
132   
133    Flags = ["-Wall"]
134   
135    output = open(compPath + 'Makefile.am','w')
136    output.writelines(header + "\n")
137    self.info2str(output,"AM_CXXFLAGS = ",Flags,1)
138     
139    BuiltSources = []
140    CleanFiles = []
141    tempIntList = []
142    nodist = []
143    for x in comp.ports:
144        #if x.interface.name in tempIntList:
145        if x.interface.filename in tempIntList:
146           continue
147##        BuiltSources.append(x.interface.name+'SK.cpp')
148##        BuiltSources.append(x.interface.name+'.idl')
149##        CleanFiles.append(x.interface.name+'SK.cpp')
150##        CleanFiles.append(x.interface.name+'.idl')
151##        CleanFiles.append(x.interface.name+'.h')
152##        nodist.append(x.interface.name+'SK.cpp')
153##        tempIntList.append(x.interface.name)
154        BuiltSources.append(x.interface.filename+'SK.cpp')
155        BuiltSources.append(x.interface.filename+'.idl')
156        CleanFiles.append(x.interface.filename+'SK.cpp')
157        CleanFiles.append(x.interface.filename+'.idl')
158        CleanFiles.append(x.interface.filename+'.h')
159        nodist.append(x.interface.filename+'SK.cpp')
160        tempIntList.append(x.interface.filename)
161     
162    self.info2str(output,"BUILT_SOURCES = ",BuiltSources,wrapFlag=True)
163    self.info2str(output,"CLEANFILES = ",CleanFiles,1)
164     
165    tstr = "ossieName = " + comp.name + "\n"
166    output.write(tstr)
167    tstr = "bin_PROGRAMS = " + comp.name + "\n\n"
168    output.write(tstr)
169     
170    tstr = "xmldir = $(prefix)/xml/$(ossieName)\n"
171    output.write(tstr)
172    #tstr2 = comp.name + "Resource"
173    tstr2 = comp.name
174    xmlData = []
175    xmlData.append(tstr2 + ".prf.xml")
176    xmlData.append(tstr2 + ".scd.xml")
177    xmlData.append(tstr2 + ".spd.xml")
178    self.info2str(output,"dist_xml_DATA = ",xmlData,1,wrapFlag=True)
179     
180    tstr = comp.name + "_SOURCES = " + comp.name+".cpp " + comp.name+".h "
181    tstr += "main.cpp port_impl.cpp port_impl.h\n"
182    output.write(tstr)   
183    self.info2str(output,"nodist_"+comp.name+"_SOURCES = ",nodist,1)
184   
185    output.close()
186
187  def info2str(self, outfile, staticStr, mylist, extraLine=0,wrapFlag=False):
188    tstr = staticStr
189    mycount = 0
190    wrap = False
191    if len(mylist) > 5 or wrapFlag == True:
192        wrap = True
193
194    for x in mylist:
195      tstr = tstr + x + " "
196      mycount += 1
197      if mycount%2 == 0 and wrap and mylist.index(x) != len(mylist)-1:
198        tstr = tstr + "\\\n"
199 
200    tstr = tstr + "\n"
201    for x in range(extraLine):
202      tstr = tstr + "\n"
203
204    outfile.write(tstr)
205
206  ##############################################################################
207  ## genConfigureACFiles - calls writeConfAC for appropriate locations
208  ##############################################################################
209  def genConfigureACFiles(self,installPath="/sdr/sca"):
210    if installPath[-1] == '/':
211        installPath = installPath[0:-1] 
212     
213    tmpPath = self.path + self.active_wave.name + '/'
214    self.writeConfAC(tmpPath,self.active_wave.name,self.active_wave.ace,True,installPath)
215   
216    for c in self.active_wave.components:
217        if c.AssemblyController ==  True or not c.generate:
218            continue
219        tmpPath = self.path + c.name + '/'
220        self.writeConfAC(tmpPath,c.name,c.ace,c.timing,False,installPath)
221       
222  ##############################################################################
223  ## writeConfAC - generates configure.ac files for autoconf
224  ##############################################################################
225  def writeConfAC(self, genPath, name, aceFlag, wavFlag, installPath):
226     if genPath[len(genPath)-1] != '/':
227        genPath = genPath + '/'
228     
229     output = open(genPath + 'configure.ac','w')
230     tstr = "AC_INIT(" + name + ", 0.5.0)\nAM_INIT_AUTOMAKE\n\n"
231     output.write(tstr)
232     #tstr = 'AC_PREFIX_DEFAULT("/home/sca")\n\n'
233     tstr = 'AC_PREFIX_DEFAULT("' + installPath + '")\n\n'
234     output.write(tstr)
235     tstr = "AC_PROG_CXX\nAC_PROG_INSTALL\nAC_PROG_MAKE_SET\n\n"
236     output.write(tstr)
237     tstr = "AC_HEADER_SYS_WAIT\n\nAC_FUNC_FORK\n\n"
238     output.write(tstr)
239     #tstr = "AC_HAVE_XERCES_C\nAC_CORBA_ORB\nAC_CORBA_OMNIEVENTS\n\n"
240     #tstr = "AC_CORBA_ORB\n\n"
241     #output.write(tstr)
242
243     tstr = 'AC_LANG_PUSH([C++])\n\n'
244     output.write(tstr)
245
246     tstr = 'AC_CHECK_LIB([omniORB4], [main], [], [AC_MSG_ERROR([cannot find omniORBi4 library])])\n'
247     output.write(tstr)
248     tstr = 'AC_CHECK_LIB([omnithread], [main], [], [AC_MSG_ERROR([cannot find omnithread library])])\n'
249     output.write(tstr)
250     tstr = 'AC_CHECK_LIB([omniDynamic4], [main], [], [AC_MSG_ERROR([cannot find omniDynamic4 library])])\n'
251     output.write(tstr)
252     tstr = 'AC_CHECK_HEADERS([omniORB4/CORBA.h], [], [AC_MSG_ERROR([cannot find omniORB4 header files])])\n\n'
253     output.write(tstr)
254
255     # TODO: only include standard interfacesi AC_CHECK lines for components
256     if True:
257        tstr = 'AC_CHECK_LIB([standardInterfaces], [main], [], [AC_MSG_ERROR([cannot find standardInterfaces])])\n'
258        output.write(tstr)
259        tstr = 'AC_CHECK_HEADERS([standardinterfaces/complexShort.h], [], [AC_MSG_ERROR([cannot find standardInterfaces header files])])\n\n'
260        output.write(tstr)
261
262     # TODO: Add support for sigproc
263     if False:
264         tstr = 'AC_CHECK_LIB([sigproc], [main], [], [AC_MSG_ERROR([cannot find sigproc library])])\n'
265         output.write(tstr)
266         tstr = 'AC_CHECK_HEADERS([sigproc/SigProc.h], [], [AC_MSG_ERROR([cannot find sigproc library header files])])\n\n'
267         output.write(tstr)
268
269     tstr = 'AC_LANG_POP\n\n'
270     output.write(tstr)
271
272     tstr = 'export PKG_CONFIG_PATH="$PKG_CONFIG_PATH:/usr/local/lib/pkgconfig"\n'
273     output.write(tstr)
274     tstr = "PKG_CHECK_MODULES(OSSIE, ossie >= 0.0.1,,exit)\n"
275     output.write(tstr)
276     tstr = 'CXXFLAGS="$CXXFLAGS $OSSIE_CFLAGS"\nLIBS="$LIBS $OSSIE_LIBS"\n'
277     output.write(tstr)
278     tstr = 'IDL_FLAGS="$OSSIE_CFLAGS"\nAC_SUBST(IDL_FLAGS)\n\n'
279     output.write(tstr)
280     
281     if aceFlag == True:
282         tstr = 'PKG_CHECK_MODULES(ACE, ACE >= 5.4.7)\n'
283         tstr = tstr + 'AC_SUBST(ACE_CFLAGS)\nAC_SUBST(ACE_LIBS)\nLIBS="$LIBS $ACE_LIBS"\n\n'
284         output.write(tstr)
285     
286     tstr = "AC_CONFIG_FILES(Makefile"     
287     if wavFlag == True:
288        for x in self.active_wave.components:
289            if x.AssemblyController and x.generate:
290                tstr2 = " " + x.name + "/Makefile"
291                tstr = tstr + tstr2
292           
293     tstr = tstr + ")\n\n"
294     output.write(tstr)
295
296     tstr = "AC_OUTPUT\n"
297     output.write(tstr)
298
299     output.close()
300   
301  ##############################################################################     
302  ## This function generates the cpp and h files for each component:
303  ## component.h, component.cpp, main.cpp, port_impl.h, and port_impl.cpp
304  ##############################################################################     
305  def genCompFiles(self,comp):
306      #for x in self.active_wave.components:
307        # generate the .h files for each component
308        inputH = open('generate/templates/custom_ports/sampleComp.h','r')
309        outputH = open(self.path + comp.name + "/" + comp.name + ".h",'w')
310        self.addGPL(outputH,comp.name)
311        for line in inputH.readlines():
312          l_out = line.replace("__CLASS_DEF__",comp.name.upper()+"_IMPL_H")
313          l_out = l_out.replace("__Class_name__",comp.name+"_i")
314          if l_out.find("__PORT_DECL__") != -1:
315              self.writePortDecl(outputH,comp)
316              continue
317          if l_out.find("__ACE_INCLUDES__") != -1:
318              if comp.ace == True:
319                  l_out = '#include "ace/Task.h"\n'
320              else:
321                  continue
322          if l_out.find("__ACE_INHERIT__") != -1:
323              if comp.ace == True:
324                  l_out = l_out.replace("__ACE_INHERIT__",", public ACE_Task<ACE_MT_SYNCH>")
325              else:
326                  l_out = l_out.replace("__ACE_INHERIT__","")
327          if l_out.find("__ACE_SVC_DECL__") != -1:
328              if comp.ace == True:
329                  l_out = l_out.replace("__ACE_SVC_DECL__",'int svc(void);\n        size_t queue_size;')
330              else:
331                  continue   
332          if l_out.find("__FRIEND_DECL__") != -1:
333              l_out = l_out.replace("__FRIEND_DECL__","")
334              self.writeFriendDecl(outputH,comp)
335              continue
336                   
337          outputH.write(l_out)
338         
339        inputH.close()
340        outputH.close()
341       
342        # generate the .cpp files for each component
343        inputCPP = open('generate/templates/custom_ports/sampleComp.cpp','r')
344        outputCPP = open(self.path + comp.name + "/" + comp.name + ".cpp",'w')
345        self.addGPL(outputCPP,comp.name)
346        for line in inputCPP.readlines():
347          l_out = line.replace("__IncludeFile__",comp.name)
348          l_out = l_out.replace("__Class_name__",comp.name+"_i")
349          #l_out = l_out.replace("__NS_name__","ossie" + comp.name+"Resource")
350          if l_out.find("__PORT_INST__") != -1:
351              self.writePortInst(outputCPP,comp)
352              continue
353          if l_out.find("__GET_PORT__") != -1:
354              self.writeGetPort(outputCPP,comp)
355              continue
356          if l_out.find("__DEL_PORT__") != -1:
357              self.writeDelPort(outputCPP,comp)
358              continue
359          if l_out.find("__ACE_SVC_PORTS__") != -1:
360              self.writeACESvcPorts(outputCPP,comp)
361              continue
362          if l_out.find("__ACE_SVC_DEF__") != -1:
363              if comp.ace == True:
364                  self.writeACESvcDef(outputCPP,comp,'component',comp.timing, comp)
365              continue             
366          outputCPP.write(l_out)
367         
368        inputCPP.close()
369        outputCPP.close()
370       
371        # generate the main.cpp files for each component
372        inputMain = open('generate/templates/custom_ports/sampleMain.cpp','r')
373        outputMain = open(self.path + comp.name + "/main.cpp",'w')
374        self.addGPL(outputMain,comp.name)
375       
376        for line in inputMain.readlines():
377          l_out = line.replace("__IncludeFile__",comp.name)
378          l_out = l_out.replace("__Class_name__",comp.name+"_i")
379          l_out = l_out.replace("__CLASS_VAR__",comp.name.lower())
380          if l_out.find("__CLASS_VAR_ACE__") != -1:
381              if comp.ace == True:
382                  l_out = l_out.replace("__CLASS_VAR_ACE__",comp.name.lower())
383              else:
384                  continue         
385          if l_out.find("__NAME_SPACE__") != -1:
386              ns_list = []
387              for p in comp.ports:
388                  if p.interface.nameSpace not in ns_list:
389                      ns_list.append(p.interface.nameSpace)
390              l_out = ''
391              for tmpns in ns_list:
392                  l_out += 'using namespace ' + tmpns + ';\n'
393
394          outputMain.write(l_out)
395         
396        inputMain.close()
397        outputMain.close()
398       
399        # generate the port_impl.h file
400        inputPortImpl = open('generate/templates/custom_ports/port_impl.h','r')
401        outputPortImpl = open(self.path + comp.name + "/port_impl.h",'w')
402        self.addGPL(outputPortImpl,comp.name)
403        portSample_p = open('generate/templates/custom_ports/port_sample_p.h','r')
404        portSample_u = open('generate/templates/custom_ports/port_sample_u.h','r')
405        for line in inputPortImpl.readlines():
406            l_out = line.replace("__IncludeFile__",comp.name)
407            if l_out.find("__ACE_INCLUDES__") != -1:
408              if comp.ace == True:
409                  l_out = '#include "ace/Task.h"\n'
410              else:
411                  continue
412            if l_out.find("__TIMING_DECL_AND_INCLUDES__") != -1:
413              if comp.timing == True:
414                  l_out = 'using namespace std;\n#ifndef time_signal_message_H\n#define time_signal_message_H\ntypedef struct {\n\tchar component_name[255];\n\tchar port_name[255];\n\tchar function_name[255];\n\tchar description[255];\n\tlong time_s;\n\tlong time_us;\n\tlong number_samples;\n} time_signal_message;\n#endif\n'
415              else:
416                  l_out = ''
417            if l_out.find("__PORT_DECL__") != -1:
418              self.writePortImplDecl(outputPortImpl,portSample_p,portSample_u,comp)
419              continue         
420            outputPortImpl.write(l_out)
421           
422        inputPortImpl.close()
423        outputPortImpl.close()
424        portSample_p.close()
425        portSample_u.close()
426       
427        # generate the port_impl.cpp file
428        inputPortImpl = open('generate/templates/custom_ports/port_impl.cpp','r')
429        outputPortImpl = open(self.path + comp.name + "/port_impl.cpp",'w')
430        self.addGPL(outputPortImpl,comp.name)
431        portSample_p = open('generate/templates/custom_ports/port_sample_p.cpp','r')
432        portSample_u = open('generate/templates/custom_ports/port_sample_u.cpp','r')
433        for line in inputPortImpl.readlines():
434            l_out = line
435            if l_out.find("__PORT_DEF__") != -1:
436              self.writePortImplDef(outputPortImpl,portSample_p,portSample_u,comp)
437              continue
438            outputPortImpl.write(l_out)
439           
440        inputPortImpl.close()
441        outputPortImpl.close()
442        portSample_p.close()
443        portSample_u.close()
444       
445    # Copy some required files into the main directory
446    #  os.system('cp generate/basic_xml/* ' + self.path)
447    #  os.system('cp generate/wavLoader.py ' + self.path)
448
449  def writePortImplDecl(self, output,portSample_p,portSample_u,c):
450    """ This function writes port implementation declarations for the port_impl.h file"""
451    intList = []
452    for x in c.ports:
453        if x.interface.filename in intList:
454            continue
455        ts = '#include "' + x.interface.filename + '.h"\n'
456        intList.append(x.interface.filename)
457        output.write(ts)
458    ts = '\n';output.write(ts);
459    intList = []
460    for x in c.ports:
461        found_match = False
462        for int_tup in intList:
463            if x.interface.name == int_tup[0]:
464                if x.type == int_tup[1]:
465                    found_match = True
466                    break
467        if found_match:
468            continue
469        #if x.interface.name in intList:
470        #    continue
471        if x.type == "Uses":
472            portSample = portSample_u
473        else:
474            portSample = portSample_p
475        portSample.seek(0)
476        intList.append((x.interface.name, x.type))
477        for line in portSample.readlines():
478            l_out = line.replace("__IN_PORT__",x.p_cname)
479            l_out = l_out.replace("__INT_TYPE__",x.interface.name)
480            l_out = l_out.replace("__NAME_SPACE__",x.interface.nameSpace)
481            l_out = l_out.replace("__OUT_PORT__",x.u_cname)
482            l_out = l_out.replace("__IN_CLASS__",x.p_cname)
483            l_out = l_out.replace("__OUT_CLASS__",x.u_cname)
484            if l_out.find("__OPERATION__") != -1:
485              self.writeOperation(output,x.interface,port=c)
486              continue
487            if l_out.find("__ACE_INHERIT__") != -1:
488              if c.ace == True:
489                  l_out = l_out.replace("__ACE_INHERIT__",", public ACE_Task<ACE_MT_SYNCH>")
490              else:
491                  l_out = l_out.replace("__ACE_INHERIT__","")
492            if l_out.find("__TIMING_BUFFER_LENGTH__") != -1:
493              if (c.timing==True):
494                if (x.interface.name=='timingStatus'):
495                  l_out = l_out.replace("__TIMING_BUFFER_LENGTH__",'#define NUMBER_TIMING_MESSAGE_BUFFER        100')
496                else:
497                  l_out = l_out.replace("__TIMING_BUFFER_LENGTH__", '');
498              else:
499                l_out = l_out.replace("__TIMING_BUFFER_LENGTH__", '');
500            if l_out.find("__TIMING_DECL__") != -1:
501              if (c.timing==True):
502                if (x.interface.name=='timingStatus'):
503                  l_out = l_out.replace("__TIMING_DECL__",'void send_timing_message(string component_name, string port_name, string function_name, string description, long number_samples);')
504                else:
505                  l_out = l_out.replace("__TIMING_DECL__",'')
506              else:
507                l_out = l_out.replace("__TIMING_DECL__",'')
508            if l_out.find("__TIMING_VAR__") != -1:
509              if (c.timing==True):
510                if (x.interface.name=='timingStatus'):
511                  l_out = l_out.replace("__TIMING_VAR__",'time_signal_message message_buffer[NUMBER_TIMING_MESSAGE_BUFFER];\n    int message_buffer_write_idx;\n    omni_mutex writing_to_timing_buffer;\n    omni_semaphore *data_is_ready;')
512                else:
513                  l_out = l_out.replace("__TIMING_VAR__",'')
514              else:
515                l_out = l_out.replace("__TIMING_VAR__",'')
516            if l_out.find("__ACE_SVC_DECL__") != -1:
517              if (c.ace == True):
518                  l_out = l_out.replace("__ACE_SVC_DECL__",'int svc(void);')
519              else:
520                  l_out = l_out.replace("__ACE_SVC_DECL__",'')
521            if l_out.find("__COMP_ARG__") != -1:
522                if c.type == "resource":
523                    l_out = l_out.replace("__COMP_ARG__",c.name+"_i *_"+c.name.lower())
524                else:
525                    l_out = l_out.replace("__COMP_ARG__","")
526            if l_out.find("__COMP_REF_DECL__") != -1:
527                if c.type == "resource":
528                    l_out = l_out.replace("__COMP_REF_DECL__",c.name+"_i *"+c.name.lower()+";")
529                else:
530                    l_out = l_out.replace("__COMP_REF_DECL__","")
531               
532            output.write(l_out)
533
534  def writePortImplDef(self,output,portSample_p,portSample_u,c):
535    """ This function writes port implementation definitions for the port_impl.cpp file"""
536    intList = []   
537    for x in c.ports:
538        found_match = False
539        for int_tup in intList:
540            if x.interface.name == int_tup[0]:
541                if x.type == int_tup[1]:
542                    found_match = True
543                    break
544        if found_match:
545            continue
546        #if x.interface.name in intList:
547        #    continue
548        if x.type == "Uses":
549            portSample = portSample_u
550        else:
551            portSample = portSample_p
552        portSample.seek(0)
553        intList.append((x.interface.name, x.name))
554        for line in portSample.readlines():
555            l_out = line.replace("__IN_PORT__",x.p_cname)
556            l_out = l_out.replace("__INT_TYPE__",x.interface.name)
557            l_out = l_out.replace("__NAME_SPACE__",x.interface.nameSpace)
558            l_out = l_out.replace("__OUT_PORT__",x.u_cname)
559            if l_out.find("__OPERATION__") != -1:
560              l_out = l_out.replace("__OPERATION__",'')
561              l_out = l_out.replace("\n",'')
562              self.writeOperation(output,x.interface,prefix=l_out,cppFlag=True,in_name=c.name.lower(),using_ace=c.ace,comp=c,port=x)
563              continue
564            if l_out.find("__ACE_SVC_DEF__") != -1:
565              if c.ace == True:
566                  self.writeACESvcDef(output,x,'port',c.timing, c)
567              continue
568            if l_out.find("__TIMING_MESSAGE_DEF__") != -1:
569              if (c.timing == True) & (x.interface.name=='timingStatus'):
570                  self.writeTimingMessageDef(output,x,'port')
571              continue
572            if l_out.find("__COMP_ARG__") != -1:
573                if c.type == "resource":
574                    l_out = l_out.replace("__COMP_ARG__",c.name+"_i *_"+c.name.lower())
575                else:
576                    l_out = l_out.replace("__COMP_ARG__","")
577            if l_out.find("__COMP_REF_DEF__") != -1:
578                if c.type == "resource":
579                    l_out = l_out.replace("__COMP_REF_DEF__",c.name.lower()+" = _"+c.name.lower()+";")
580                else:
581                    l_out = l_out.replace("__COMP_REF_DEF__","")
582            if l_out.find("__INIT_VARS_DEF__") != -1:
583                if (c.type == "resource") & (x.interface.name=='timingStatus'):
584                    l_out = l_out.replace("__INIT_VARS_DEF__","message_buffer_write_idx = 0;\n    data_is_ready = new omni_semaphore(0);")
585                else:
586                    l_out = l_out.replace("__INIT_VARS_DEF__","")
587            output.write(l_out)
588
589  def writePortDecl(self, output,c):
590    """ This function writes the corba declarations of the ports to the component header file"""
591    inCount = 0; outCount=0;
592    for x in c.ports:
593        if x.type == "Provides":
594            ts = " "*8 + x.cname + " " + "*inPort" + str(inCount) + "_servant;\n"
595            output.write(ts)
596            inCount += 1
597    ts = "\n"; output.write(ts)
598    for x in c.ports:
599        if x.type == "Uses":
600            ts = " "*8 + x.cname + " " + "*outPort" + str(outCount) + "_servant;\n"
601            output.write(ts)
602            outCount += 1
603    ts = "\n"; output.write(ts)
604    inCount = 0; outCount=0;
605    for x in c.ports:
606        if x.type == "Provides":
607            ts = " "*8 + x.interface.nameSpace + "::" + x.interface.name + "_var " + "inPort" + str(inCount) + "_var;\n"
608            output.write(ts)
609            inCount += 1
610    ts = "\n"; output.write(ts)
611    for x in c.ports:
612        if x.type == "Uses":
613            ts = " "*8 + "CF::Port_var " + "outPort" + str(outCount) + "_var;\n"
614            ts += " "*8 + "bool outPort" + str(outCount) + "_active;\n"
615            ts += " "*8 + "size_t outPort" + str(outCount) + "_queue_size;\n"
616            output.write(ts)
617            outCount += 1
618    ts = " "*8 + "bool component_alive;\n\n" + " "*8 + "string naming_service_name;\n"; output.write(ts)
619   
620  def writePortInst(self,output,c):
621    """ This function writes the port instantiations to the component cpp file"""
622    inCount = 0; outCount=0;
623    for x in c.ports:
624        if x.type == "Provides":
625            ts = " "*4 + "inPort" + str(inCount) + "_servant" + " = new " + x.cname + "(this);\n"
626            output.write(ts)
627            ts = " "*4 + "inPort" + str(inCount) + "_var = inPort" + str(inCount)+ "_servant->_this();\n"
628            output.write(ts)
629            inCount += 1
630    ts = "\n"; output.write(ts)
631    for x in c.ports:
632        if x.type == "Uses":
633            ts = " "*4 + "outPort" + str(outCount) + "_servant" + " = new " + x.cname + "(this);\n"
634            output.write(ts)
635            ts = " "*4 + "outPort" + str(outCount) + "_var = outPort" + str(outCount)+ "_servant->_this();\n"
636            ts += " "*4 + "outPort" + str(outCount) + "_active = false;\n"
637            ts += " "*4 + "outPort" + str(outCount) + "_queue_size = DEFAULT_QUEUE_BLOCK_SIZE;\n"
638            output.write(ts)
639            outCount += 1
640    ts = "\n"; output.write(ts)
641    ts = " "*4 + "queue_size = DEFAULT_QUEUE_BLOCK_SIZE;\n\n" + " "*4 + "component_alive = true;\n\n" + " "*4 + "naming_service_name = label;\n"; output.write(ts)
642   
643  def writeGetPort(self,output,c):
644    """ This function writes the getPort functionality to the component cpp file"""
645    inCount = 0; outCount=0;
646    flag = True
647    for x in c.ports:
648        if x.type == "Provides":
649            if flag:
650                ts = " "*4 + 'if (strcmp(_id,"' + x.name + '") == 0) {\n'
651            else:
652                ts = " "*4 + 'else if (strcmp(_id,"' + x.name + '") == 0) {\n'
653            output.write(ts)
654#            ts = " "*8 + "return inPort" + str(inCount) + "_var;\n"
655            ts = " "*8 + "return " + x.interface.nameSpace + "::" + x.interface.name
656            ts += "::_duplicate(inPort" + str(inCount) + "_var);\n"
657            ts += " "*4 + "}\n"
658            output.write(ts)
659            inCount += 1
660    ts = "\n"; output.write(ts)
661    for x in c.ports:
662        if x.type == "Uses":
663            if flag:
664                ts = " "*4 + 'if (strcmp(_id,"' + x.name + '") == 0) {\n'
665            else:
666                ts = " "*4 + 'else if (strcmp(_id,"' + x.name + '") == 0) {\n'
667            output.write(ts)
668            ts = " "*8 + "outPort" + str(outCount) + "_active = true;\n"
669            ts += " "*8 + "return CF::Port::_duplicate(outPort" + str(outCount) + "_var);\n"
670            ts += " "*4 + "}\n"
671            output.write(ts)
672            outCount += 1
673    ts = "\n"; output.write(ts)
674    ts = " "*4 + 'return NULL;\n'; output.write(ts)
675   
676  def writeDelPort(self,output,c):
677    """ This function writes the destructor functionality (for ports) to the component cpp file"""
678    inCount = 0; outCount=0;
679    flag = True
680    for x in c.ports:
681        if x.type == "Provides":
682            ts = " "*4 + "delete inPort" + str(inCount) + "_servant;\n"
683            output.write(ts)
684            inCount += 1
685    ts = "\n"; output.write(ts)
686    for x in c.ports:
687        if x.type == "Uses":
688            ts = " "*4 + "delete outPort" + str(outCount) + "_servant;\n"
689            output.write(ts)
690            outCount += 1
691    ts = "\n"; output.write(ts)
692   
693##  def writeACESvcPorts(self,output,c):
694##    """ This function writes the svc port functionality to the component cpp file"""
695##    outCount=0;
696##    for x in c.ports:
697##        if x.type == "Uses":
698##            ts = " "*4 + "outPort" + str(outCount) + "_servant->activate();\n"
699##            output.write(ts)
700##            outCount += 1
701##    ts = "\n"; output.write(ts) 
702   
703  def writeACESvcDef(self, output,c,type,timing_flag, comp=''):
704    """ This function writes the implementation of the svn() function for a given component"""
705    if type == 'component':
706        ts = 'int ' + c.name + '_i::svc(void)\n{\n'
707        output.write(ts)
708        ts = " "*4 + '/* Start outgoing port threads */\n'
709        output.write(ts)
710        outCount=0;
711        for x in c.ports:
712            if x.type == "Uses":
713                ts = " "*4 + "outPort" + str(outCount) + "_servant->activate();\n"; output.write(ts)
714                outCount += 1
715        ts = "\n"; output.write(ts)
716        ts = " "*4 + 'std::vector<double> d1_data_double;\n'; output.write(ts)
717        ts = " "*4 + 'std::vector<float> d1_data_float;\n'; output.write(ts)
718        ts = " "*4 + 'std::vector<short> d1_data_short;\n'; output.write(ts)
719        ts = " "*4 + 'std::vector<float> d2_data_double;\n'; output.write(ts)
720        ts = " "*4 + 'std::vector<double> d2_data_float;\n'; output.write(ts)
721        ts = " "*4 + 'std::vector<short> d2_data_short;\n'; output.write(ts)
722        ts = " "*4 + 'ACE_Message_Block *mb;\n'; output.write(ts)
723        ts = " "*4 + '/* Main function loop */\n'; output.write(ts)
724        ts = " "*4 + 'while(component_alive)\n' + " "*4 + '{\n'; output.write(ts)
725        ts = " "*8 + "ACE_Time_Value getq_time_out = ACE_OS::gettimeofday();\n"; output.write(ts)
726        ts = " "*8 + "getq_time_out += 1;\n"; output.write(ts)
727        ts = " "*8 + "if(getq(mb, &getq_time_out) >= 0) {\n"; output.write(ts)
728        ts = " "*12 + "unsigned int buffer_size=mb->length();\n"; output.write(ts)
729        ts = " "*12 + "unsigned short data_type;\n"; output.write(ts)
730        ts = " "*12 + "ACE_OS::memmove( (char*)&data_type, mb->rd_ptr(), sizeof(unsigned short));\n"; output.write(ts)
731        ts = " "*12 + "mb->rd_ptr(sizeof(unsigned short));\n"; output.write(ts)
732        ts = " "*12 + "buffer_size=buffer_size - sizeof(unsigned short);\n"; output.write(ts)
733        ts = " "*12 + "unsigned int packet_size = 0;\n"; output.write(ts)
734        ts = " "*12 + "std::vector<double> data_I;\n"; output.write(ts)
735        ts = " "*12 + "std::vector<double> data_Q;\n"; output.write(ts)
736        ts = " "*12 + "// I've arbitrarily decided to use doubles as my working type inside the component\n"; output.write(ts)
737        ts = " "*12 + "//       the working type is implementation-specific\n"; output.write(ts)
738        ts = " "*12 + "switch(data_type) {\n"; output.write(ts)
739        ts = " "*16 + "case 1:\n"; output.write(ts)
740        ts = " "*20 + "// this is for complex double\n"; output.write(ts)
741        ts = " "*20 + "packet_size=buffer_size/(sizeof(double)*2);\n"; output.write(ts)
742        ts = " "*20 + "{\n"; output.write(ts)
743        ts = " "*24 + "std::vector <double> vals(packet_size*2);\n"; output.write(ts)
744        ts = " "*24 + "ACE_OS::memmove( (char*)&vals[0], mb->rd_ptr(), buffer_size);\n"; output.write(ts)
745        ts = " "*24 + "data_I.resize(packet_size);\n"; output.write(ts)
746        ts = " "*24 + "data_Q.resize(packet_size);\n"; output.write(ts)
747        ts = " "*24 + "for (unsigned int i = 0; i<packet_size; i++) {\n"; output.write(ts)
748        ts = " "*28 + "data_I[i] = vals[i];\n"; output.write(ts)
749        ts = " "*28 + "data_Q[i] = vals[i+packet_size];\n"; output.write(ts)
750        ts = " "*24 + "}\n"; output.write(ts)
751        ts = " "*20 + "}\n"; output.write(ts)
752        ts = " "*20 + "break;\n"; output.write(ts)
753        ts = " "*16 + "case 2:\n"; output.write(ts)
754        ts = " "*20 + "// this is for complex float\n"; output.write(ts)
755        ts = " "*20 + "packet_size=buffer_size/(sizeof(float)*2);\n"; output.write(ts)
756        ts = " "*20 + "{\n"; output.write(ts)
757        ts = " "*24 + "std::vector <float> vals(packet_size*2);\n"; output.write(ts)
758        ts = " "*24 + "ACE_OS::memmove( (char*)&vals[0], mb->rd_ptr(), buffer_size);\n"; output.write(ts)
759        ts = " "*24 + "data_I.resize(packet_size);\n"; output.write(ts)
760        ts = " "*24 + "data_Q.resize(packet_size);\n"; output.write(ts)
761        ts = " "*24 + "for (unsigned int i = 0; i<packet_size; i++) {\n"; output.write(ts)
762        ts = " "*28 + "data_I[i] = vals[i];\n"; output.write(ts)
763        ts = " "*28 + "data_Q[i] = vals[i+packet_size];\n"; output.write(ts)
764        ts = " "*24 + "}\n"; output.write(ts)
765        ts = " "*20 + "}\n"; output.write(ts)
766        ts = " "*20 + "break;\n"; output.write(ts)
767        ts = " "*16 + "case 3:\n"; output.write(ts)
768        ts = " "*20 + "// this is for complex short\n"; output.write(ts)
769        ts = " "*20 + "packet_size=buffer_size/(sizeof(short)*2);\n"; output.write(ts)
770        ts = " "*20 + "{\n"; output.write(ts)
771        ts = " "*24 + "std::vector <short> vals(packet_size*2);\n"; output.write(ts)
772        ts = " "*24 + "ACE_OS::memmove( (char*)&vals[0], mb->rd_ptr(), buffer_size);\n"; output.write(ts)
773        ts = " "*24 + "data_I.resize(packet_size);\n"; output.write(ts)
774        ts = " "*24 + "data_Q.resize(packet_size);\n"; output.write(ts)
775        ts = " "*24 + "for (unsigned int i = 0; i<packet_size; i++) {\n"; output.write(ts)
776        ts = " "*28 + "data_I[i] = vals[i];\n"; output.write(ts)
777        ts = " "*28 + "data_Q[i] = vals[i+packet_size];\n"; output.write(ts)
778        ts = " "*24 + "}\n"; output.write(ts)
779        ts = " "*20 + "}\n"; output.write(ts)
780        ts = " "*20 + "break;\n"; output.write(ts)
781        ts = " "*16 + "case 4:\n"; output.write(ts)
782        ts = " "*20 + "// this is for real double\n"; output.write(ts)
783        ts = " "*20 + "packet_size=buffer_size/(sizeof(double));\n"; output.write(ts)
784        ts = " "*20 + "{\n"; output.write(ts)
785        ts = " "*24 + "std::vector <double> vals(packet_size);\n"; output.write(ts)
786        ts = " "*24 + "ACE_OS::memmove( (char*)&vals[0], mb->rd_ptr(), buffer_size);\n"; output.write(ts)
787        ts = " "*24 + "data_I.resize(packet_size);\n"; output.write(ts)
788        ts = " "*24 + "data_Q.resize(packet_size);\n"; output.write(ts)
789        ts = " "*24 + "for (unsigned int i = 0; i<packet_size; i++) {\n"; output.write(ts)
790        ts = " "*28 + "data_I[i] = vals[i];\n"; output.write(ts)
791        ts = " "*28 + "data_Q[i] = 0;\n"; output.write(ts)
792        ts = " "*24 + "}\n"; output.write(ts)
793        ts = " "*20 + "}\n"; output.write(ts)
794        ts = " "*20 + "break;\n"; output.write(ts)
795        ts = " "*16 + "case 5:\n"; output.write(ts)
796        ts = " "*20 + "// this is for real float\n"; output.write(ts)
797        ts = " "*20 + "packet_size=buffer_size/(sizeof(float));\n"; output.write(ts)
798        ts = " "*20 + "{\n"; output.write(ts)
799        ts = " "*24 + "std::vector <float> vals(packet_size);\n"; output.write(ts)
800        ts = " "*24 + "ACE_OS::memmove( (char*)&vals[0], mb->rd_ptr(), buffer_size);\n"; output.write(ts)
801        ts = " "*24 + "data_I.resize(packet_size);\n"; output.write(ts)
802        ts = " "*24 + "data_Q.resize(packet_size);\n"; output.write(ts)
803        ts = " "*24 + "for (unsigned int i = 0; i<packet_size; i++) {\n"; output.write(ts)
804        ts = " "*28 + "data_I[i] = vals[i];\n"; output.write(ts)
805        ts = " "*28 + "data_Q[i] = 0;\n"; output.write(ts)
806        ts = " "*24 + "}\n"; output.write(ts)
807        ts = " "*20 + "}\n"; output.write(ts)
808        ts = " "*20 + "break;\n"; output.write(ts)
809        ts = " "*16 + "case 6:\n"; output.write(ts)
810        ts = " "*20 + "// this is for real short\n"; output.write(ts)
811        ts = " "*20 + "packet_size=buffer_size/(sizeof(short));\n"; output.write(ts)
812        ts = " "*20 + "{\n"; output.write(ts)
813        ts = " "*24 + "std::vector <short> vals(packet_size);\n"; output.write(ts)
814        ts = " "*24 + "ACE_OS::memmove( (char*)&vals[0], mb->rd_ptr(), buffer_size);\n"; output.write(ts)
815        ts = " "*24 + "data_I.resize(packet_size);\n"; output.write(ts)
816        ts = " "*24 + "data_Q.resize(packet_size);\n"; output.write(ts)
817        ts = " "*24 + "for (unsigned int i = 0; i<packet_size; i++) {\n"; output.write(ts)
818        ts = " "*28 + "data_I[i] = vals[i];\n"; output.write(ts)
819        ts = " "*28 + "data_Q[i] = 0;\n"; output.write(ts)
820        ts = " "*24 + "}\n"; output.write(ts)
821        ts = " "*20 + "}\n"; output.write(ts)
822        ts = " "*20 + "break;\n"; output.write(ts)
823        ts = " "*12 + "}\n"; output.write(ts)
824        #ts = " "*8 + "}\n"; output.write(ts)
825        ts = " "*12 + "mb->release();\n"; output.write(ts)
826        ts = " "*12 + "/*******************************************************************\n"; output.write(ts)
827        ts = " "*24 + "Insert functional code here\n"; output.write(ts)
828        ts = " "*12 + "*******************************************************************/\n\n"; output.write(ts)
829        ts = " "*12 + "/******************************************************************/\n\n"; output.write(ts)
830        ts = " "*12 + "// Prepare data for output\n"; output.write(ts)
831        ts = " "*12 + "d1_data_double.resize(packet_size);\n"; output.write(ts)
832        ts = " "*12 + "d1_data_float.resize(packet_size);\n"; output.write(ts)
833        ts = " "*12 + "d1_data_short.resize(packet_size);\n"; output.write(ts)
834        ts = " "*12 + "d2_data_double.resize(packet_size*2);\n"; output.write(ts)
835        ts = " "*12 + "d2_data_float.resize(packet_size*2);\n"; output.write(ts)
836        ts = " "*12 + "d2_data_short.resize(packet_size*2);\n\n"; output.write(ts)
837        ts = " "*12 + "for (unsigned int i=0; i<packet_size; i++) {\n"; output.write(ts)
838        ts = " "*16 + "d1_data_double[i] = data_I[i];\n"; output.write(ts)
839        ts = " "*16 + "d1_data_float[i] = data_I[i];\n"; output.write(ts)
840        ts = " "*16 + "d1_data_short[i] = (short)data_I[i];\n"; output.write(ts)
841        ts = " "*16 + "d2_data_double[i] = data_I[i];\n"; output.write(ts)
842        ts = " "*16 + "d2_data_double[i+packet_size] = data_Q[i];\n"; output.write(ts)
843        ts = " "*16 + "d2_data_float[i] = data_I[i];\n"; output.write(ts)
844        ts = " "*16 + "d2_data_float[i+packet_size] = data_Q[i];\n"; output.write(ts)
845        ts = " "*16 + "d2_data_short[i] = (short)data_I[i];\n"; output.write(ts)
846        ts = " "*16 + "d2_data_short[i+packet_size] = (short)data_Q[i];\n"; output.write(ts)
847        ts = " "*12 + "}\n"; output.write(ts)
848        outCount=0;
849        for x in c.ports:
850            if (x.type == "Uses") & ((x.interface.name == 'realDouble')|(x.interface.name == 'realFloat')|(x.interface.name == 'realShort')|(x.interface.name == 'complexDouble')|(x.interface.name == 'complexFloat')|(x.interface.name == 'complexShort')):
851                ts = " "*12 + "if (outPort" + str(outCount) + "_active) {\n"; output.write(ts)
852                if x.interface.name == 'realDouble':
853                        DATA_TYPE_BEING_USED = 'double'
854                        VECTOR_COUNT = '1'
855                        VECTOR_NAME = 'd1_data_double'
856                if x.interface.name == 'realFloat':
857                        DATA_TYPE_BEING_USED = 'float'
858                        VECTOR_COUNT = '1'
859                        VECTOR_NAME = 'd1_data_float'
860                if x.interface.name == 'realShort':
861                        DATA_TYPE_BEING_USED = 'short'
862                        VECTOR_COUNT = '1'
863                        VECTOR_NAME = 'd1_data_short'
864                if x.interface.name == 'complexDouble':
865                        DATA_TYPE_BEING_USED = 'double'
866                        VECTOR_COUNT = '2'
867                        VECTOR_NAME = 'd2_data_double'
868                if x.interface.name == 'complexFloat':
869                        DATA_TYPE_BEING_USED = 'float'
870                        VECTOR_COUNT = '2'
871                        VECTOR_NAME = 'd2_data_float'
872                if x.interface.name == 'complexShort':
873                        DATA_TYPE_BEING_USED = 'short'
874                        VECTOR_COUNT = '2'
875                        VECTOR_NAME = 'd2_data_short'
876                ts = " "*16 + "ACE_Message_Block *message = new ACE_Message_Block (packet_size*" + VECTOR_COUNT + "*sizeof(" + DATA_TYPE_BEING_USED + "));\n"; output.write(ts)
877                ts = " "*16 + "message->copy((const char*)&" + VECTOR_NAME + "[0], packet_size*" + VECTOR_COUNT + "*sizeof(" + DATA_TYPE_BEING_USED + "));\n"; output.write(ts)
878                ts = " "*16 + "size_t message_length = packet_size*" + VECTOR_COUNT + "*sizeof(" + DATA_TYPE_BEING_USED + ");\n"; output.write(ts)
879                ts = " "*16 + "size_t available_space = outPort" + str(outCount) + "_servant->msg_queue()->message_bytes();\n"; output.write(ts)
880                ts = " "*16 + "if (available_space<=(outPort" + str(outCount) + "_queue_size+message_length)) {\n"; output.write(ts)
881                ts = " "*20 + "outPort" + str(outCount) + "_queue_size+=QUEUE_BLOCK_SIZE;\n"; output.write(ts)
882                ts = " "*20 + "outPort" + str(outCount) + "_servant->water_marks (ACE_IO_Cntl_Msg::SET_HWM, outPort" + str(outCount) + "_queue_size);\n"; output.write(ts)
883                ts = " "*16 + "}\n"; output.write(ts)
884                ts = " "*16 + "if (outPort" + str(outCount) + "_servant->putq(message) == -1) {\n"; output.write(ts)
885                ts = " "*20 + "//  this is where a message for issues with the putq would appear\n"; output.write(ts)
886                ts = " "*16 + "}\n"; output.write(ts)
887                ts = " "*12 + "}\n"; output.write(ts)
888                outCount += 1
889        ts = " "*8 + "}\n"; output.write(ts)
890        ts = " "*8 + "/* Polling rate, slow CPU spinning */\n"; output.write(ts)
891        ts = " "*8 + "//ACE_OS::sleep (ACE_Time_Value (1));\n"; output.write(ts)
892        ts = " "*4 + '}\n\n' + " "*4 + 'return 0;\n}\n'; output.write(ts)
893       
894    if type == 'port':
895        #ts = 'int ' + c.u_cname + '::svc(void)\n{\n'; output.write(ts)
896        #ts = " "*4 + 'ACE_Message_Block *mb;\n\n'; output.write(ts)
897        #ts = " "*4 + 'while(1)\n' + " "*4 + '{\n' + " "*8 + 'if (getq(mb) == -1)\n'
898        #output.write(ts)
899        #ts = " "*8 + '{\n' + " "*12 + 'ACE_ERROR_RETURN ((LM_ERROR, ' + r'"%p\n",'
900        #ts = ts + ' "getq"), -1);\n'
901        #output.write(ts)
902        #ts = " "*8 + '}\n\n' + " "*8 + '/* _complexShort->pushPacket(); */\n\n'
903        #output.write(ts)
904        #ts = " "*8 + '/* Release message block */\n' + " "*8 + 'mb->release();\n'
905        #output.write(ts)
906        #ts = " "*4 + '}\n' + " "*4 + 'return 0;\n}\n'
907        #output.write(ts)
908                # the following stuff is a work in progress
909                #       it needs to be reconciled with the contents of the actual port
910                #       This will be interesting for control ports instead of data ports
911                #       in the case of control ports, it will likely need a slightly different structure
912        #print c.interface.name
913        ts = 'int ' + c.u_cname + '::svc(void)\n{\n'; output.write(ts)
914        if ((c.interface.name == 'realDouble')|(c.interface.name == 'realFloat')|(c.interface.name == 'realShort')|(c.interface.name == 'complexDouble')|(c.interface.name == 'complexFloat')|(c.interface.name == 'complexShort')):
915                ts = " "*4 + 'ACE_Message_Block *mb;\n'; output.write(ts)
916                if c.interface.name == 'realDouble':
917                        DATA_TYPE_BEING_USED = 'double'
918                        DATA_TYPE_USED = 'Double'
919                        ARGUMENT_LIST_FOR_PUSH = ' I'
920                if c.interface.name == 'realFloat':
921                        DATA_TYPE_BEING_USED = 'float'
922                        DATA_TYPE_USED = 'Float'
923                        ARGUMENT_LIST_FOR_PUSH = ' I'
924                if c.interface.name == 'realShort':
925                        DATA_TYPE_BEING_USED = 'short'
926                        DATA_TYPE_USED = 'Short'
927                        ARGUMENT_LIST_FOR_PUSH = ' I'
928                if c.interface.name == 'complexDouble':
929                        DATA_TYPE_BEING_USED = 'double'
930                        DATA_TYPE_USED = 'Double'
931                        ARGUMENT_LIST_FOR_PUSH = ' I, Q'
932                if c.interface.name == 'complexFloat':
933                        DATA_TYPE_BEING_USED = 'float'
934                        DATA_TYPE_USED = 'Float'
935                        ARGUMENT_LIST_FOR_PUSH = ' I, Q'
936                if c.interface.name == 'complexShort':
937                        DATA_TYPE_BEING_USED = 'short'
938                        DATA_TYPE_USED = 'Short'
939                        ARGUMENT_LIST_FOR_PUSH = ' I, Q'
940                ts = " "*4 + 'vector < ' + DATA_TYPE_BEING_USED + ' > vals;\n'; output.write(ts)
941                ts = " "*4 + 'PortTypes::' + DATA_TYPE_USED + 'Sequence ' + ARGUMENT_LIST_FOR_PUSH +';\n\n'; output.write(ts)
942                ts = " "*4 + 'while(1)\n' + " "*8 + '{\n'; output.write(ts)
943                ts = " "*8 + 'ACE_Time_Value getq_time_out = ACE_OS::gettimeofday();\n'; output.write(ts)
944                ts = " "*8 + 'getq_time_out += 1;\n'; output.write(ts)
945                ts = " "*8 + 'if(getq(mb, &getq_time_out) >= 0) {\n'; output.write(ts)
946                portCount = 0
947                if c.interface.name == 'realDouble':
948                        NUMBER_OF_VECTORS = '1'
949                if c.interface.name == 'realFloat':
950                        NUMBER_OF_VECTORS = '1'
951                if c.interface.name == 'realShort':
952                        NUMBER_OF_VECTORS = '1'
953                if c.interface.name == 'complexDouble':
954                        NUMBER_OF_VECTORS = '2'
955                if c.interface.name == 'complexFloat':
956                        NUMBER_OF_VECTORS = '2'
957                if c.interface.name == 'complexShort':
958                        NUMBER_OF_VECTORS = '2'
959                for individual_port in comp.ports:
960                        if individual_port.type == "Uses":
961                                if individual_port.interface.name == 'timingStatus':
962                                        ts = " "*12 + "if (" + comp.name.lower() + "->outPort" + str(portCount) + '_active) {\n'; output.write(ts)
963                                        ts = " "*16 + comp.name.lower() + "->outPort" + str(portCount) + '_servant->send_timing_message(' + comp.name.lower() + '->naming_service_name, "' + c.name + '", "pushPacket", "begin", mb->length()/(sizeof('+ DATA_TYPE_BEING_USED +')*'+ NUMBER_OF_VECTORS +'));\n'; output.write(ts)
964                                        ts = " "*12 + '}\n'; output.write(ts)
965                                portCount += 1
966                ts = " "*12 + 'unsigned int buffer_size=mb->length();\n'; output.write(ts)
967                ts = " "*12 + 'unsigned int packet_size=buffer_size/(sizeof(' + DATA_TYPE_BEING_USED + ')*' + NUMBER_OF_VECTORS + ');\n'; output.write(ts)
968                ts = " "*12 + 'vals.resize(packet_size*' + NUMBER_OF_VECTORS + ');\n'; output.write(ts)
969                if c.interface.name == 'realDouble':
970                        ts = " "*12 + 'I.length(packet_size);\n'; output.write(ts)
971                if c.interface.name == 'realFloat':
972                        ts = " "*12 + 'I.length(packet_size);\n'; output.write(ts)
973                if c.interface.name == 'realShort':
974                        ts = " "*12 + 'I.length(packet_size);\n'; output.write(ts)
975                if c.interface.name == 'complexDouble':
976                        ts = " "*12 + 'I.length(packet_size);\n'+" "*12 + 'Q.length(packet_size);\n'; output.write(ts)
977                if c.interface.name == 'complexFloat':
978                        ts = " "*12 + 'I.length(packet_size);\n'+" "*12 + 'Q.length(packet_size);\n'; output.write(ts)
979                if c.interface.name == 'complexShort':
980                        ts = " "*12 + 'I.length(packet_size);\n'+" "*12 + 'Q.length(packet_size);\n'; output.write(ts)
981                ts = " "*12 + 'ACE_OS::memmove( (char*)&vals[0], mb->rd_ptr(), buffer_size);\n'; output.write(ts)
982                ts = " "*12 + 'for (unsigned int i=0; i<packet_size; i++) {\n'; output.write(ts)
983                if c.interface.name == 'realDouble':
984                        ts = " "*16 + 'I[i]=vals[i];\n'; output.write(ts)
985                if c.interface.name == 'realFloat':
986                        ts = " "*16 + 'I[i]=vals[i];\n'; output.write(ts)
987                if c.interface.name == 'realShort':
988                        ts = " "*16 + 'I[i]=vals[i];\n'; output.write(ts)
989                if c.interface.name == 'complexDouble':
990                        ts = " "*16 + 'I[i]=vals[i];\n'; output.write(ts)
991                        ts = " "*16 + 'Q[i]=vals[i+packet_size];\n'; output.write(ts)
992                if c.interface.name == 'complexFloat':
993                        ts = " "*16 + 'I[i]=vals[i];\n'; output.write(ts)
994                        ts = " "*16 + 'Q[i]=vals[i+packet_size];\n'; output.write(ts)
995                if c.interface.name == 'complexShort':
996                        ts = " "*16 + 'I[i]=vals[i];\n'; output.write(ts)
997                        ts = " "*16 + 'Q[i]=vals[i+packet_size];\n'; output.write(ts)
998                ts = " "*12 + '}\n'; output.write(ts)
999                ts = " "*12 + 'for (unsigned int i = 0; i < outPorts.size(); i++) {\n'; output.write(ts)
1000                ts = " "*16 + 'outPorts[i].port_var->pushPacket( ' + ARGUMENT_LIST_FOR_PUSH + ' );\n'; output.write(ts)
1001                ts = " "*12 + '}\n'; output.write(ts)
1002                portCount = 0
1003                for individual_port in comp.ports:
1004                        if individual_port.type == "Uses":
1005                                if individual_port.interface.name == 'timingStatus':
1006                                        ts = " "*12 + "if (" + comp.name.lower() + "->outPort" + str(portCount) + '_active) {\n'; output.write(ts)
1007                                        ts = " "*16 + comp.name.lower() + "->outPort" + str(portCount) + '_servant->send_timing_message(' + comp.name.lower() + '->naming_service_name, "' + c.name + '", "pushPacket", "end", mb->length()/(sizeof('+ DATA_TYPE_BEING_USED +')*'+ NUMBER_OF_VECTORS +'));\n'; output.write(ts)
1008                                        ts = " "*12 + '}\n'; output.write(ts)
1009                                portCount += 1
1010                ts = " "*12 + 'mb->release();\n'; output.write(ts)
1011                ts = " "*8 + '}\n'; output.write(ts)
1012                ts = " "*4 + '}\n' + " "*4 + 'return 0;\n}\n'
1013                output.write(ts)
1014        else:
1015                if timing_flag & (c.interface.name=='timingStatus'):
1016                        ts = " "*4 + 'dataOut_timingStatus_i *output_port = this;\n'; output.write(ts)
1017                        ts = " "*4 + 'int message_buffer_read_idx = 0;\n'; output.write(ts)
1018                        ts = " "*4 + '\n'; output.write(ts)
1019                        ts = " "*4 + 'while(1) {\n'; output.write(ts)
1020                        ts = " "*8 + 'output_port->data_is_ready->wait();\n'; output.write(ts)
1021                        ts = " "*8 + 'for (unsigned int i = 0; i < output_port->outPorts.size(); i++) {\n'; output.write(ts)
1022                        ts = " "*12 + 'output_port->outPorts[i].port_var->send_timing_event(output_port->message_buffer[message_buffer_read_idx].component_name,\n'; output.write(ts)
1023                        ts = " "*16 + 'output_port->message_buffer[message_buffer_read_idx].port_name,\n'; output.write(ts)
1024                        ts = " "*16 + 'output_port->message_buffer[message_buffer_read_idx].function_name,\n'; output.write(ts)
1025                        ts = " "*16 + 'output_port->message_buffer[message_buffer_read_idx].description,\n'; output.write(ts)
1026                        ts = " "*16 + 'output_port->message_buffer[message_buffer_read_idx].time_s,\n'; output.write(ts)
1027                        ts = " "*16 + 'output_port->message_buffer[message_buffer_read_idx].time_us,\n'; output.write(ts)
1028                        ts = " "*16 + 'output_port->message_buffer[message_buffer_read_idx].number_samples);\n'; output.write(ts)
1029                        ts = " "*8 + '}\n'; output.write(ts)
1030                        ts = " "*8 + 'message_buffer_read_idx++;\n'; output.write(ts)
1031                        ts = " "*8 + 'message_buffer_read_idx = message_buffer_read_idx%NUMBER_TIMING_MESSAGE_BUFFER;\n'; output.write(ts)
1032                        ts = " "*4 + '}\n'; output.write(ts)
1033                        ts = " "*4 + 'return 0;\n'; output.write(ts)
1034                        ts = '}\n'; output.write(ts)
1035                else:
1036                        ts = " "*4 + 'return 0;\n' + '}\n'; output.write(ts)
1037   
1038  def writeTimingMessageDef(self, output,c,type):
1039    if type == 'port':
1040        ts = 'void ' + c.u_cname + '::send_timing_message(string component_name, string port_name, string function_name, string description, long number_samples) {\n'; output.write(ts)
1041        ts = " "*4 + 'writing_to_timing_buffer.lock();\n'; output.write(ts)
1042        ts = " "*4 + 'struct timeval tv;\n'; output.write(ts)
1043        ts = " "*4 + 'struct timezone tz;\n'; output.write(ts)
1044        ts = " "*4 + 'gettimeofday(&tv, &tz);\n'; output.write(ts)
1045        ts = " "*4 + 'strcpy(message_buffer[message_buffer_write_idx].component_name, component_name.c_str());\n'; output.write(ts)
1046        ts = " "*4 + 'strcpy(message_buffer[message_buffer_write_idx].port_name, port_name.c_str());\n'; output.write(ts)
1047        ts = " "*4 + 'strcpy(message_buffer[message_buffer_write_idx].function_name, function_name.c_str());\n'; output.write(ts)
1048        ts = " "*4 + 'strcpy(message_buffer[message_buffer_write_idx].description, description.c_str());\n'; output.write(ts)
1049        ts = " "*4 + 'message_buffer[message_buffer_write_idx].time_s = tv.tv_sec;\n'; output.write(ts)
1050        ts = " "*4 + 'message_buffer[message_buffer_write_idx].time_us = tv.tv_usec;\n'; output.write(ts)
1051        ts = " "*4 + 'message_buffer[message_buffer_write_idx].number_samples = number_samples;\n'; output.write(ts)
1052        ts = " "*4 + 'message_buffer_write_idx++;\n'; output.write(ts)
1053        ts = " "*4 + 'message_buffer_write_idx = message_buffer_write_idx%NUMBER_TIMING_MESSAGE_BUFFER;\n'; output.write(ts)
1054        ts = " "*4 + 'writing_to_timing_buffer.unlock();\n'; output.write(ts)
1055        ts = " "*4 + 'data_is_ready->post();\n'; output.write(ts)
1056        ts = '}\n'; output.write(ts)
1057
1058  def writeOperation(self,output,i,prefix='',cppFlag=False,in_name='',using_ace=False,comp='',port=''):
1059    """ Writes the declaration or definition of an operation (pushPacket) to
1060        the port_impl.h and port_impl.cpp files respectively """
1061    ocount = 0
1062    for o in i.operations:
1063       
1064
1065        ocount += 1
1066        if cppFlag:
1067            if ocount > 1:
1068                ts = "\n" + o.returnType + ' ' + prefix + o.name + '('
1069                tscxx = "\n" + o.cxxReturnType + ' ' + prefix + o.name + '('
1070            else:
1071                ts = o.returnType + ' ' + prefix + o.name + '('
1072                tscxx = o.cxxReturnType + ' ' + prefix + o.name + '('
1073        else:
1074            ts = prefix + " "*4 + o.returnType + ' ' + o.name + '('
1075            tscxx = prefix + " "*4 + o.cxxReturnType + ' ' + o.name + '('
1076       
1077        first = True
1078        for p in o.params:
1079            _USE_AMPERSAND_ = ''
1080            _USE_CONST_ = 'const '
1081            _USE__OUT_ = ''
1082            if p.direction == 'out':
1083                if len(p.dataType) > 8 and p.dataType[-8:] != 'Sequence':
1084                    _USE_CONST_ = ''
1085                    _USE_AMPERSAND_ = '&'
1086                if len(p.dataType) <= 8:
1087                    _USE_CONST_ = ''
1088                    _USE_AMPERSAND_ = '&'
1089            if p.direction == 'in' and len(p.dataType) > 8 and p.dataType[-8:] == 'Sequence':
1090                _USE_AMPERSAND_ = '&'
1091            if p.direction == 'inout' and len(p.dataType) > 8 and p.dataType[-8:] == 'Sequence':
1092                _USE_CONST_ = ''
1093                _USE_AMPERSAND_ = '&'
1094            if p.direction == 'out' and len(p.dataType) > 8 and p.dataType[-8:] == 'Sequence':
1095                _USE__OUT_ = '_out'
1096
1097            if not first:
1098                ts += ','
1099                tscxx += ','
1100            else:
1101                first = False
1102            ts += _USE_CONST_ + p.dataType + _USE__OUT_ + ' ' + _USE_AMPERSAND_ + p.name
1103            tscxx += p.cxxType + ' ' + p.name
1104        #if len(o.params) != 0:
1105        if cppFlag:
1106            ts += ')\n'
1107            tscxx += ')\n'
1108        else:
1109            ts += ');\n'
1110            tscxx += ');\n'
1111#        output.write(ts)
1112        output.write(tscxx)
1113       
1114        if cppFlag:
1115                #ts = "{\n" + " "*4 + "unsigned int len = " + "hello" + ".length();\n"; output.write(ts)
1116                #ts = "{\n\n" + " "*4 + "/* Data flow and processing goes here */\n\n"; output.write(ts)
1117                if using_ace:
1118                        if len(o.params)>0:
1119                                if _USE__OUT_ == '' :
1120                                        if ((o.params[0].dataType == 'PortTypes::DoubleSequence')|(o.params[0].dataType == 'PortTypes::FloatSequence')|(o.params[0].dataType == 'PortTypes::ShortSequence')):
1121                                                portCount = 0
1122                                                ts = "{\n"; output.write(ts)
1123                                                for individual_port in comp.ports:
1124                                                        if individual_port.type == "Uses":
1125                                                                if individual_port.interface.name == 'timingStatus':
1126                                                                        ts = " "*4 + "if (" + comp.name.lower() + "->outPort" + str(portCount) + '_active) {\n'; output.write(ts)
1127                                                                        ts = " "*8 + comp.name.lower() + "->outPort" + str(portCount) + '_servant->send_timing_message(' + comp.name.lower() + '->naming_service_name, "' + port.name + '", "' + o.name + '", "begin", I.length());\n'; output.write(ts)
1128                                                                        ts = " "*4 + '}\n'; output.write(ts)
1129                                                                portCount += 1
1130                                                ts = " "*4 + "unsigned int len = " + o.params[0].name + ".length();\n"; output.write(ts)
1131                                                if o.params[0].dataType == 'PortTypes::DoubleSequence':
1132                                                        TYPE_NAME = 'double';
1133                                                if o.params[0].dataType == 'PortTypes::FloatSequence':
1134                                                        TYPE_NAME = 'float';
1135                                                if o.params[0].dataType == 'PortTypes::ShortSequence':
1136                                                        TYPE_NAME = 'short';
1137                                                if len(o.params) == 1:
1138                                                        NUMBER_VECS = '1'
1139                                                        if o.params[0].dataType == 'PortTypes::DoubleSequence':
1140                                                                DATA_TYPE = '4';
1141                                                        if o.params[0].dataType == 'PortTypes::FloatSequence':
1142                                                                DATA_TYPE = '5';
1143                                                        if o.params[0].dataType == 'PortTypes::ShortSequence':
1144                                                                DATA_TYPE = '6';
1145                                                if len(o.params) == 2:
1146                                                        NUMBER_VECS = '2'
1147                                                        if o.params[0].dataType == 'PortTypes::DoubleSequence':
1148                                                                DATA_TYPE = '1';
1149                                                        if o.params[0].dataType == 'PortTypes::FloatSequence':
1150                                                                DATA_TYPE = '2';
1151                                                        if o.params[0].dataType == 'PortTypes::ShortSequence':
1152                                                                DATA_TYPE = '3';
1153                                                ts = " "*4 + "vector <" + TYPE_NAME + "> data_in(len*" + NUMBER_VECS + ");\n"; output.write(ts)
1154                                                ts = " "*4 + "char *buffer;\n"; output.write(ts)
1155                                                ts = " "*4 + "buffer = new char[len*" + NUMBER_VECS + "*sizeof(" + TYPE_NAME + ")+sizeof(unsigned short)];\n\n"; output.write(ts)
1156                                                ts = " "*4 + "for (unsigned int i = 0; i<len; i++) {\n"; output.write(ts)
1157                                                if len(o.params) == 1:
1158                                                        ts = " "*8 + "data_in[i] = " + o.params[0].name + "[i];\n"; output.write(ts)
1159                                                if len(o.params) == 2:
1160                                                        ts = " "*8 + "data_in[i] = " + o.params[0].name + "[i];\n"; output.write(ts)
1161                                                        ts = " "*8 + "data_in[i+len] = " + o.params[1].name + "[i];\n"; output.write(ts)
1162                                                ts = " "*4 + "}\n"; output.write(ts)
1163                                                ts = " "*4 + "unsigned short data_type = " + DATA_TYPE + ";\n"; output.write(ts)
1164                                                ts = " "*4 + "memcpy(buffer, &data_type, sizeof(unsigned short));\n"; output.write(ts)
1165                                                ts = " "*4 + "memcpy(&buffer[sizeof(unsigned short)], (char *)&data_in[0], len*" + NUMBER_VECS + "*sizeof(" + TYPE_NAME + ")+sizeof(unsigned short));\n"; output.write(ts)
1166                                                ts = "\n" + " "*4 + "ACE_Message_Block *message = new ACE_Message_Block (len*" + NUMBER_VECS + "*sizeof(" + TYPE_NAME + ")+sizeof(unsigned short));\n"; output.write(ts)
1167                                                ts = " "*4 + "message->copy((const char*)&buffer[0], len*" + NUMBER_VECS + "*sizeof(" + TYPE_NAME + ")+sizeof(unsigned short));\n"; output.write(ts)
1168                                                ts = " "*4 + "size_t message_length = len*" + NUMBER_VECS + "*sizeof(" + TYPE_NAME + ")+sizeof(unsigned short);\n"; output.write(ts)
1169                                                ts = " "*4 + "size_t available_space = " + in_name + "->msg_queue()->message_bytes();\n"; output.write(ts)
1170                                                ts = " "*4 + "if (available_space<=(" + in_name + "->queue_size+message_length)) {\n"; output.write(ts)
1171                                                ts = " "*8 + "" + in_name + "->queue_size+=QUEUE_BLOCK_SIZE;\n"; output.write(ts)
1172                                                ts = " "*8 + "" + in_name + "->water_marks (ACE_IO_Cntl_Msg::SET_HWM," + in_name + "->queue_size);\n"; output.write(ts)
1173                                                ts = " "*4 + "}\n"; output.write(ts)
1174                                                ts = " "*4 + "if (" + in_name + "->putq(message) == -1) {\n"; output.write(ts)
1175                                                ts = " "*8 + "// this is where there would be a message about the putq failing\n"; output.write(ts)
1176                                                ts = " "*4 + "}\n"; output.write(ts)
1177                                                portCount = 0
1178                                                for individual_port in comp.ports:
1179                                                        if individual_port.type == "Uses":
1180                                                                if individual_port.interface.name == 'timingStatus':
1181                                                                        ts = " "*4 + "if (" + comp.name.lower() + "->outPort" + str(portCount) + '_active) {\n'; output.write(ts)
1182                                                                        ts = " "*8 + comp.name.lower() + "->outPort" + str(portCount) + '_servant->send_timing_message(' + comp.name.lower() + '->naming_service_name, "' + port.name + '", "' + o.name + '", "end", I.length());\n'; output.write(ts)
1183                                                                        ts = " "*4 + '}\n'; output.write(ts)
1184                                                                portCount += 1
1185                                                ts = " "*4 + "\ndelete buffer;\n}\n"; output.write(ts)
1186                                                #ts += " "*4 + "/* if using ACE:\n\n" + " "*7
1187                                                #ts += "ACE_Message_Block *mb;\n" + " "*7 + "putq(mb);\n"
1188                                                #ts += " "*4 + "*/\n\n}\n"
1189                                                #output.write(ts)
1190                                        else:
1191                                                ts = "{\n\n}\n"; output.write(ts)
1192                                else:
1193                                        ts = "{\n\n}\n"; output.write(ts)
1194                        else:
1195                                ts = "{\n\n}\n"; output.write(ts)
1196                else:
1197                        ts = "{\n\n}\n"; output.write(ts)
1198       
1199  def writeFriendDecl(self,output,c):
1200      friendList = []
1201      for p in c.ports:
1202          if p.type == "Uses":
1203              if p.u_cname not in friendList:
1204                  friendList.append(p.u_cname)
1205          if p.type == "Provides":
1206              if p.p_cname not in friendList:
1207                  friendList.append(p.p_cname)
1208                 
1209      for x in friendList:
1210          ts = " "*4 + "friend class " + x + ";\n"
1211          output.write(ts)
1212     
1213
1214  def addGPL(self,outFile,name):
1215      inFile = open('generate/gpl_preamble','r')
1216      for line in inFile.readlines():
1217          l_out = line.replace("__COMP_NAME__",name)
1218          outFile.write(l_out)
1219       
1220      inFile.close()
1221         
1222       
1223  def cleanUp(self):
1224      # Move the AssemblyController to the waveform Dir
1225      for c in self.active_wave.components:
1226        if c.AssemblyController == True and c.generate:
1227            os.system('mv ' + self.path + c.name + ' ' + self.path + self.active_wave.name)
1228
1229       
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