root/ossiedev/branches/mcarrick/VHDL/carry_lookahead_adder/carry_lookahead_adder_tb.vhd @ 8216

-- test bench for CLA

library ieee;
use ieee.std_logic_1164.all;

entity test_CLA is
end entity test_CLA;

architecture test_CLA_tb of test_CLA is

        component carry_lookahead_adder is
                generic ( numBits       : integer := 4
                );
                port (  a               : in    std_logic_vector(numBits-1 downto 0);
                                b               : in    std_logic_vector(numBits-1 downto 0);
                                cIn             : in    std_logic;
                                s               : out   std_logic_vector(numBits-1 downto 0);
                                cOut    : out   std_logic
                );
        end component carry_lookahead_adder;
        
        signal A, B, S : std_logic_vector(3 downto 0);
        signal CIN, COUT : std_logic;
        
        begin

                CLA_inst : carry_lookahead_adder
                        generic map ( numBits => 4
                        )
                        port map (      a               => A,
                                                b               => B,
                                                cIn             => CIN,
                                                s               => S,
                                                cOut    => COUT
                        );

                enter_inputs : process
                begin

                        A <= x"0";
                        B <= x"0";
                        CIN <= '0';

                        wait for 5 ns;
                        A <= x"0";
                        B <= x"1";
                        CIN <= '1';

                        wait for 5 ns;
                        A <= x"2";
                        B <= x"2";
                        CIN <= '0';

                        wait for 5 ns;
                        A <= x"F";
                        B <= x"1";
                        CIN <= '0';

                        wait for 5 ns;
                        A <= x"F";
                        B <= x"F";
                        CIN <= '1';

                        wait for 5 ns;
                        A <= x"A";
                        B <= x"5";
                        CIN <= '1';

                        wait for 5 ns;

                end process enter_inputs;

end architecture test_CLA_tb;