root/ossiedev/branches/mcarrick/VHDL/carry_lookahead_adder/carry_lookahead_adder_tb.vhd @ 8225

-- test bench for CLA

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test_CLA is
end entity test_CLA;

architecture test_CLA_tb of test_CLA is

        component carry_lookahead_adder is
                generic ( numBits       : integer := 4
                );
                port (  a               : in    std_logic_vector(numBits-1 downto 0);
                                b               : in    std_logic_vector(numBits-1 downto 0);
                                cIn             : in    std_logic;
                                s               : out   std_logic_vector(numBits-1 downto 0);
                                cOut    : out   std_logic
                );
        end component carry_lookahead_adder;
        
        signal A, B : std_logic_vector(3 downto 0) := (others => '0');
        signal S : std_logic_vector(3 downto 0);
        signal CIN, COUT : std_logic;

        signal result : std_logic_vector(4 downto 0);
        signal check : std_logic_vector(4 downto 0);

        begin

                CLA_inst : carry_lookahead_adder
                        generic map ( numBits => 4
                        )
                        port map (      a               => A,
                                                b               => B,
                                                cIn             => CIN,
                                                s               => S,
                                                cOut    => COUT
                        );

                -- calculate 5 bit result from circuit
                result <= COUT & S;
                -- calculate 5 bit result independently
                check <= std_logic_vector(unsigned("0" & A) + unsigned("0" & B) + ("000" & CIN));

                enter_inputs : process
                begin

                        -- loop for CIN
                        for i in 0 to 1 loop

                                -- set CIN test values
                                if (i = 0) then
                                        CIN <= '0';
                                else
                                        CIN <= '1';
                                end if;
                        
                                -- loop for A
                                for iA in 0 to 15 loop

                                        if (iA = 0) then
                                                A <= (others => '0');
                                        elsif (iA > 0) then
                                                A <= std_logic_vector(unsigned(A) + 1);
                                        end if;

                                        -- loop for B
                                        for iB in 0 to 15 loop
                                        
                                                if (iB = 0) then
                                                        B <= (others => '0');
                                                elsif (iB > 0) then
                                                        B <= std_logic_vector(unsigned(B) + 1);
                                                end if;

                                                wait for 1 ns;

                                                if (check /= result) then
                                                        report "The summation has been calculated incorrectly!";
                                                end if;

                                        end loop;

                                end loop;

                        end loop;

                end process enter_inputs;

end architecture test_CLA_tb;