root/ossiedev/branches/mcarrick/VHDL/full_adder_pg/full_adder_pg.vhd @ 8226

-- Adder with Propogate and Generate Functions
--
-- This component is slightly different from a 
-- real full adder which computes both the sum
-- and the carry out. This computes only the sum
-- and the propagate and generate functions for
-- use in a carry look ahead adder.

library ieee;
use ieee.std_logic_1164.all;

entity full_adder_pg is
        port (  a               : in    std_logic;
                        b               : in    std_logic;
                        cIn             : in    std_logic;
                        s               : out   std_logic;
                        p               : out   std_logic;
                        g               : out   std_logic
        );
end entity full_adder_pg;

architecture full_adder_pg_behav of full_adder_pg is

        begin

                -- only calculate sum
                s <= (a xor b) xor cIn;

                -- calculate the propagate and generate functions
                g <= a and b;
                p <= a or b;

end architecture full_adder_pg_behav;