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Changeset 11094

Timestamp:

04/05/12 13:02:33 (14 months ago)

Author:

june

Message:

Completing test on USRP1, USRP2

Location:

ossiedev/branches/june/trunk/platform/USRP_UHD

Files:

: 4 modified

src/USRP_UHD.cpp (modified) (10 diffs)
src/USRP_UHD.h (modified) (4 diffs)
src/port_impl.cpp (modified) (15 diffs)
xml/USRP_UHD.scd.xml (modified) (2 diffs)

Legend:

: Unmodified
: Added
: Removed

ossiedev/branches/june/trunk/platform/USRP_UHD/src/USRP_UHD.cpp

r11034	r11094
26	26	#include <vector>
27	27	#include <complex>
	28	#include <boost/program_options.hpp>
	29	#include <boost/format.hpp>
	30	#include <boost/thread.hpp>
28	31
29	32	#include "ossie/cf.h"
…	…
39	42	set_rx_packet_count(-1),
40	43	rx_packet_count(1024),
41		rx_packet_size(~~256~~),
	44	rx_packet_size(8192),
42	45	rx_data_size(2),
43	46	number_of_channels(1),
…	…
50	53	{
51	54	// Create USRP_UHD Control ports for TX and RX
52		rx_control_port = new USRP_UHD_RX_Control_i(this, "U2_RX_Control", "DomainName1");
53		tx_control_port = new USRP_UHD_TX_Control_i(this, "U2_TX_Control", "DomainName1");
	55	rx_control_port = new USRP_UHD_RX_Control_i(this, "UHD_RX_Control", "DomainName1");
	56	tx_control_port = new USRP_UHD_TX_Control_i(this, "UHD_TX_Control", "DomainName1");
54	57
55	58	// Create the ports for TX data
56		tx_data_port = new standardInterfaces_i::complexShort_p("U2_TX_Data", "DomainName1");
	59	for(int i=0;i<MAX_TX_CHANNEL;i++)
	60	tx_data_ports[i] = new standardInterfaces_i::complexShort_p(boost::str(boost::format("UHD_TX_Data_%d") % (i+1)).c_str(), "DomainName1");
57	61
58	62	// Create the ports for RX Data
59		rx_data_1_port = new standardInterfaces_i::complexShort_u("U2_RX_Data_1", "DomainName1");
60		rx_data_2_port = new standardInterfaces_i::complexShort_u("U2_RX_Data_2", "DomainName1");
	63	for(int i=0;i<MAX_RX_CHANNEL;i++)
	64	rx_data_ports[i] = new standardInterfaces_i::complexShort_u(boost::str(boost::format("UHD_RX_Data_%d") % (i+1)).c_str(), "DomainName1");
	65
61	66	}
62	67
…	…
81	86	if (!CORBA::is_nil(p = rx_control_port->getPort(portName)))
82	87	return p._retn();
83		else if (!CORBA::is_nil(p = ~~rx_data_1~~_port->getPort(portName)))
	88	else if (!CORBA::is_nil(p = tx_control_port->getPort(portName)))
84	89	return p._retn();
85		else if (!CORBA::is_nil(p = rx_data_1_port->getPort(portName))) {
86		return p._retn();
87		} else if (!CORBA::is_nil(p = tx_control_port->getPort(portName))) {
88		return p._retn();
89		} else if (!CORBA::is_nil(p = tx_data_port->getPort(portName))) {
90		return p._retn();
	90	else {
	91	for(int i=0;i<MAX_RX_CHANNEL;i++)
	92	if (!CORBA::is_nil(p = rx_data_ports[i]->getPort(portName)))
	93	return p._retn();
	94
	95	for(int i=0;i<MAX_TX_CHANNEL;i++)
	96	if (!CORBA::is_nil(p = tx_data_ports[i]->getPort(portName)))
	97	return p._retn();
91	98	}
	99
92	100	std::cerr << "Couldn't find port " << portName << "Throwing exception" << std::endl;
93		throw CF::PortSupplier::UnknownPort();
	101	// throw CF::PortSupplier::UnknownPort();
94	102	}
95	103
…	…
100	108	DEBUG(1, USRP_UHD, "Creating the usrp device with: "<< args)
101	109	sdev = uhd::usrp::multi_usrp::make(args);
102		dev = sdev->get_device();
	110	dev = sdev->get_device();//uhd::device::make(args);
	111	probe_usrp();
	112	rx_control_port->set_number_of_channels(1);
	113	tx_control_port->set_number_of_channels(1);
103	114	sdev->set_rx_antenna("RX2");
104	115	sdev->set_rx_antenna("TX/RX");
…	…
127	138	}
128	139
	140	void USRP_UHD_i::rx_error_helper(uhd::rx_metadata_t::error_code_t error)
	141	{
	142	switch(error){
	143	case uhd::rx_metadata_t::ERROR_CODE_NONE:
	144	break;
	145	case uhd::rx_metadata_t::ERROR_CODE_TIMEOUT:
	146	DEBUG(2, USRP_UHD, "Got timeout before all samples received, possible packet loss")
	147	break;
	148	case uhd::rx_metadata_t::ERROR_CODE_LATE_COMMAND:
	149	DEBUG(2, USRP_UHD, "UHD::ERROR_CODE_LATE_COMMAND")
	150	break;
	151	case uhd::rx_metadata_t::ERROR_CODE_BROKEN_CHAIN:
	152	DEBUG(2, USRP_UHD, "UHD::ERROR_CODE_BROKEN_CHAIN")
	153	break;
	154	case uhd::rx_metadata_t::ERROR_CODE_OVERFLOW:
	155	//DEBUG(2, USRP_UHD, "UHD::ERROR_CODE_OVERFLOW")
	156	break;
	157	case uhd::rx_metadata_t::ERROR_CODE_ALIGNMENT:
	158	DEBUG(2, USRP_UHD, "UHD::ERROR_CODE_ALIGNMENT")
	159	break;
	160	case uhd::rx_metadata_t::ERROR_CODE_BAD_PACKET:
	161	DEBUG(2, USRP_UHD, "UHD::ERROR_CODE_BAD_PACKET")
	162	break;
	163	default:
	164	DEBUG(3, USRP_UHD, "Got Error Code 0x"<<error)
	165	}
	166	}
129	167
130	168	void USRP_UHD_i::rx_data_process()
…	…
146	184	sdev->issue_stream_cmd(stream_cmd);
147	185
148		uhd::stream_args_t stream_args("sc16");
	186	uhd::stream_args_t stream_args("sc16"); //complex floats
149	187	stream_args.args["noclear"] = "1";
	188	for (size_t chan = 0; chan < rx_channels; chan++)
	189	stream_args.channels.push_back(chan); //linear mapping
150	190	uhd::rx_streamer::sptr rx_stream = sdev->get_rx_stream(stream_args);
151
	191	DEBUG(3, USRP_UHD, "Rx Channels = " << rx_channels)
152	192	PortTypes::ShortSequence I;
153	193	PortTypes::ShortSequence Q;
154	194
155	195	///\TODO Make sure rx_packet_size is >= than USRP_UHD_MIN_RX_SAMPLES!!!!!
156		rx_buff.resize(rx_packet_size);
	196	std::vector<std::vector< std::complex<short> > > rx_buff(
	197	rx_channels, std::vector< std::complex<short> >(rx_packet_size)
	198	);
157	199	I.length(rx_packet_size);
158	200	Q.length(rx_packet_size);
	201
	202	std::vector<std::complex<short> *> rx_buff_ptrs;
	203	for (size_t i = 0; i < rx_buff.size(); i++)
	204	rx_buff_ptrs.push_back(&rx_buff[i].front());
159	205
160	206	DEBUG(3, USRP_UHD, "RX packet count " << rx_packet_count)
…	…
168	214	did_rx = true;
169	215	}
	216	//DEBUG(9, USRP_UHD, "issue cmd")
170	217
171	218
172	219	//TODO get rid of num_rx_samps variable
173		size_t num_rx_samps = rx_stream->recv( &rx_buff.front(), rx_packet_size, md);
	220	size_t num_rx_samps = rx_stream->recv( rx_buff_ptrs, rx_packet_size, md);
	221	//DEBUG(9, USRP_UHD, "recv data")
174	222
175	223	//Handle UHD error codes
176		switch(md.error_code){
177		case uhd::rx_metadata_t::ERROR_CODE_NONE:
178		break;
179		case uhd::rx_metadata_t::ERROR_CODE_TIMEOUT:
180		DEBUG(3, USRP_UHD, "Got timeout before all samples received, possible packet loss")
181		break;
182		default:
183		DEBUG(3, USRP_UHD, "Got error code 0x"<<md.error_code)
	224	rx_error_helper(md.error_code);
	225
	226	for(int j=0;j<rx_channels;j++){
	227
	228	for (unsigned int i = 0; i < num_rx_samps; i++) {
	229	I[i] = (CORBA::Short) rx_buff[j][i].real();
	230	Q[i] = (CORBA::Short) rx_buff[j][i].imag();
	231	}
	232
	233	//DEBUG(9, USRP_UHD, "before push packet")
	234	rx_data_ports[j]->pushPacket(I, Q);
	235	//DEBUG(9, USRP_UHD, "after push packet")
184	236	}
185	237
186		for (unsigned int i = 0; i < num_rx_samps; i++) {
187		I[i] = (CORBA::Short) rx_buff[i].real();
188		Q[i] = (CORBA::Short) rx_buff[i].imag();
189		}
190		rx_data_1_port->pushPacket(I, Q);
	238
191	239
192	240	if (rx_packet_count != -1)
…	…
220	268	const unsigned int tx_buf_len(USRP_UHD_MAX_TX_SAMPLES);
221	269
222		uhd::stream_args_t stream_args("sc16");
	270	uhd::stream_args_t stream_args("sc16"); //complex short
223	271	stream_args.args["noclear"] = "1";
	272	for (size_t chan = 0; chan < tx_channels; chan++)
	273	stream_args.channels.push_back(chan); //linear mapping
224	274	uhd::tx_streamer::sptr tx_stream = sdev->get_tx_stream(stream_args);
225
226	275
227	276	uhd::tx_metadata_t md3;
…	…
238	287	//md.time_spec = uhd::time_spec_t((time_t)0 );
239	288
240		~~std::vector< std::complex<short int> > tx_buff(tx_buf_len);~~
241	289
242	290	DEBUG(3, USRP_UHD, "Starting tx_data_process thread.")
243	291
244	292	tx_active = true; // Cleared to stop TX in USRP_UHD_TX_Control->stop()
245
	293	size_t samps_to_send = 0;
	294	std::vector<std::complex<short> *> tx_buff_ptrs;
	295	DEBUG(3, USRP_UHD, "Max Number of Sample="<<tx_stream->get_max_num_samps())
246	296	while (tx_active) {
247		//if running half duplex mode we want to stop Rx streaming while transmitting
248		if (full_duplex == false && did_rx == true) {
249		did_rx = false;
250		uhd::rx_metadata_t md;
251		size_t num_rx_samps = dev->recv( &rx_buff.front(), rx_packet_size, md,
252		uhd::io_type_t::COMPLEX_INT16,
253		uhd::device::RECV_MODE_FULL_BUFF);
254		sdev->issue_stream_cmd(uhd::stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS);
255
	297
	298	for(int i=0;i<tx_channels;i++){
	299
	300	tx_data_ports[i]->getData(I_in, Q_in);
	301	samps_to_send = I_in->length();
	302
	303	std::vector<std::complex<short> > tx_buff(samps_to_send);
	304
	305	for (unsigned int j = 0; j < samps_to_send; ++j) {
	306	tx_buff[j] = std::complex<short int> (convertToLE((I_in)[j]),convertToLE((Q_in)[j]));
	307	}
	308
	309	tx_buff_ptrs.push_back(&tx_buff.front());
	310	tx_data_ports[i]->bufferEmptied();
256	311	}
257	312
258
259		~~tx_data_port->getData(I_in, Q_in);~~
260		~~size_t samps_to_send = I_in->length();~~
261
262		~~if(samps_to_send > tx_buf_len){~~
263		~~std::cerr << "USRP_UHD Tx Buffer Overflow. Throwing Exception"<<std::endl;~~
264		~~throw std::runtime_error("USRP_UHD buffer overflow");~~
265		}
266
267		~~for (unsigned int i = 0; i < samps_to_send; ++i) {~~
268		~~tx_buff[i] = std::complex<short int> (convertToLE((I_in)[i]),convertToLE((Q_in)[i]));~~
269		}
270
271	313	//send the entire packet (driver fragments internally)
272		size_t num_tx_samps = tx_stream->send( &tx_buff.front(), samps_to_send, md3);
273		tx_data_port->bufferEmptied();
	314	size_t num_tx_samps = tx_stream->send(tx_buff_ptrs, samps_to_send, md3);
	315
	316
274	317
275	318	}
276
277	319	DEBUG(3, USRP_UHD, "Exiting tx_data_process thread.")
278	320	tx_thread->exit();
279	321	}
	322
	323	void print_tree(const uhd::fs_path &path, uhd::property_tree::sptr tree){
	324	std::cout << path << std::endl;
	325	BOOST_FOREACH(const std::string &name, tree->list(path)){
	326	print_tree(path / name, tree);
	327	}
	328	}
	329
	330
	331	void USRP_UHD_i::probe_usrp()
	332	{
	333	DEBUG(3, USRP_UHD, "Probing daughter board of USRP..")
	334	uhd::property_tree::sptr tree = dev->get_tree();
	335	uhd::fs_path db_path, mb_path = "/mboards";
	336	mb_count = tree->list("/mboards").size();
	337	std::cout<<" The number of MB : "<<mb_count<<std::endl;
	338	for(int i=0;i<mb_count;i++){
	339	mb_path = "/mboards";
	340	mb_path = mb_path / tree->list("/mboards")[i];
	341	db_count = tree->list( mb_path / "dboards").size();
	342	std::cout<<" The number of DB slot: "<<db_count<<std::endl;
	343	for(int j=0;j<db_count;j++){
	344	db_path = mb_path / "dboards" / tree->list( mb_path / "dboards")[j];
	345	uhd::usrp::dboard_eeprom_t prom = tree->access<uhd::usrp::dboard_eeprom_t>(db_path / "tx_eeprom").get();
	346	std::cout<<" TxDB ID : "<<prom.id.to_string()<<std::endl;
	347
	348	prom = tree->access<uhd::usrp::dboard_eeprom_t>(db_path / "rx_eeprom").get();
	349	std::cout<<" RxDB ID : "<<prom.id.to_string()<<std::endl;
	350	}
	351
	352
	353	}
	354
	355	}

ossiedev/branches/june/trunk/platform/USRP_UHD/src/USRP_UHD.h

r11034	r11094
30	30
31	31	#include <uhd/usrp/multi_usrp.hpp>
	32	#include <uhd/property_tree.hpp>
	33	#include <uhd/usrp/dboard_id.hpp>
	34	#include <uhd/usrp/mboard_eeprom.hpp>
	35	#include <uhd/usrp/subdev_spec.hpp>
	36	#include <uhd/usrp/dboard_eeprom.hpp>
	37	#include <uhd/usrp/dboard_manager.hpp>
32	38
33	39	#include "ossie/cf.h"
…	…
43	49	#define ADC_RATE 100e6
44	50	#define USRP_UHD_MAX_TX_SAMPLES 4192
	51	#define MAX_TX_CHANNEL 2
	52	#define MAX_RX_CHANNEL 2
45	53
46	54	// Definitions for provides ports
…	…
173	181	USRP_UHD_TX_Control_i* tx_control_port;
174	182
175		standardInterfaces_i::complexShort_u* rx_data_1_port;
176		standardInterfaces_i::complexShort_u* rx_data_2_port;
177
178		standardInterfaces_i::complexShort_p* tx_data_port;
	183	standardInterfaces_i::complexShort_u* rx_data_ports[MAX_RX_CHANNEL];
	184	standardInterfaces_i::complexShort_p* tx_data_ports[MAX_TX_CHANNEL];
179	185
180	186	// usrp_uhd variables
181	187	uhd::usrp::multi_usrp::sptr sdev;
182	188	uhd::device::sptr dev;
183		std::vector<std::complex<short> > rx_buff;
	189
	190
184	191	omni_thread *rx_thread;
185	192	omni_thread *tx_thread;
186	193
	194	void rx_error_helper(uhd::rx_metadata_t::error_code_t error);
187	195	void rx_data_process();
188	196	void tx_data_process();
	197	void probe_usrp();
189	198
190	199	long set_rx_packet_count;
…	…
203	212	bool full_duplex;
204	213	bool did_rx;
205		};
	214
	215	size_t mb_count;
	216	size_t db_count;
	217	size_t tx_channels;
	218	size_t rx_channels;
	219
	220
	221	};

ossiedev/branches/june/trunk/platform/USRP_UHD/src/port_impl.cpp

r11039	r11094
34	34	void USRP_UHD_TX_Control_i::set_number_of_channels(CORBA::ULong nchan)
35	35	{
36		DEBUG(3, USRP_UHD, "Setting number of TX channels to " << nchan<< " is not supported");
37
	36	omni_mutex_lock l(usrp_uhd->tx_control_access);
	37	uhd::property_tree::sptr tree = usrp_uhd->dev->get_tree();
	38	uhd::fs_path db_path, mb_path = "/mboards";
	39
	40	int assigned_channel = 0;
	41	std::string subdev_spec;
	42	for(int i=0;(i<usrp_uhd->mb_count)&&(assigned_channel<nchan);i++){
	43	mb_path = "/mboards";
	44	mb_path = mb_path / tree->list("/mboards")[i];
	45
	46	for(int j=0;(j<usrp_uhd->db_count)&&(assigned_channel<nchan);j++){
	47	db_path = mb_path / "dboards" / tree->list( mb_path / "dboards")[j];
	48	uhd::usrp::dboard_eeprom_t prom = tree->access<uhd::usrp::dboard_eeprom_t>(db_path / "tx_eeprom").get();
	49	if (prom.id != uhd::usrp::dboard_id_t::none()){
	50	subdev_spec = subdev_spec + tree->list( mb_path / "dboards")[j] + ":"
	51	+ tree->list(db_path / "tx_frontends").at(0) + " ";
	52	assigned_channel++;
	53
	54	}
	55
	56
	57	}
	58	DEBUG(3, USRP_UHD, "subdev of tx channel@MB"<<i<<" = "<<subdev_spec)
	59	usrp_uhd->sdev->set_tx_subdev_spec(uhd::usrp::subdev_spec_t(subdev_spec),i);
	60
	61	}
	62	usrp_uhd->tx_channels = usrp_uhd->sdev->get_tx_num_channels();
	63	DEBUG(3, USRP_UHD, "# of Tx Channels Requested="<<nchan<<", Real="<<usrp_uhd->tx_channels)
	64	}
	65
	66	void USRP_UHD_TX_Control_i::get_number_of_channels(CORBA::ULong &num)
	67	{
38	68	///\TODO: Define if we need this interface. Number of channels is defined at transmit or receive
39
40		//omni_mutex_lock l(usrp_uhd->tx_control_access);
41
42		//usrp_uhd->usrp_uhd_ptr->set_nchannels(nchan);
43		}
44
45		void USRP_UHD_TX_Control_i::get_number_of_channels(CORBA::ULong &num)
46		{
47		///\TODO: Define if we need this interface. Number of channels is defined at transmit or receive
48		DEBUG(3, USRP_UHD, "Getting number of TX channels is not supported");
49		//omni_mutex_lock l(usrp_uhd->tx_control_access);
50
51		//num = usrp_uhd->usrp_uhd_ptr->nchannels();
	69	omni_mutex_lock l(usrp_uhd->tx_control_access);
	70	num = usrp_uhd->sdev->get_tx_num_channels();
	71	DEBUG(3, USRP_UHD, "Tx get number of channels = "<<num)
52	72	}
53	73
54	74	void USRP_UHD_TX_Control_i::get_gain_range(CORBA::ULong channel, CORBA::Float &gmin, CORBA::Float &gmax, CORBA::Float &gstep)
55	75	{
56		if (channel == 0) {
57		if (usrp_uhd->sdev) {
58		uhd::gain_range_t range = usrp_uhd->sdev->get_tx_gain_range();
59		// All values in range are in dB
60		gmin = range.start();
61		gmax = range.stop();
62		gstep = range.step();
63		}
64		} else {
65		return; ///\todo throw bad channel exception
66		}
	76	omni_mutex_lock l(usrp_uhd->tx_control_access);
	77	if (usrp_uhd->sdev) {
	78	uhd::gain_range_t range = usrp_uhd->sdev->get_tx_gain_range(channel);
	79	// All values in range are in dB
	80	gmin = range.start();
	81	gmax = range.stop();
	82	gstep = range.step();
	83	DEBUG(3, USRP_UHD, "Tx gain range = "<<range.to_pp_string())
	84	}
	85	else{
	86
	87	}
67	88	}
68	89
69	90	void USRP_UHD_TX_Control_i::set_gain(CORBA::ULong channel, CORBA::Float gain)
70	91	{
	92	omni_mutex_lock l(usrp_uhd->tx_control_access);
	93
	94	if (usrp_uhd->sdev) {
	95	usrp_uhd->sdev->set_tx_gain(gain,channel);
	96	DEBUG(3, USRP_UHD, "Tx set gain = "<<gain)
	97	}
	98	else {
	99
	100	}
	101	}
	102
	103	void USRP_UHD_TX_Control_i::get_gain(CORBA::ULong channel, CORBA::Float &gain)
	104	{
71	105	omni_mutex_lock l(usrp_uhd->tx_control_access);
72
73		if (channel == 0) {
74		if (usrp_uhd->sdev) {
75		usrp_uhd->sdev->set_tx_gain(gain);
76		}
77		} else {
78		return; ///\todo throw bad channel exception
79		}
80		}
81
82		void USRP_UHD_TX_Control_i::get_gain(CORBA::ULong channel, CORBA::Float &gain)
83		{
84		omni_mutex_lock l(usrp_uhd->tx_control_access);
85		if (channel == 0) {
86		if (usrp_uhd->sdev) {
87		gain = usrp_uhd->sdev->get_tx_gain();
88		}
89		} else {
90		return; ///\todo throw bad channel exception
91		}
	106	if (usrp_uhd->sdev) {
	107	gain = usrp_uhd->sdev->get_tx_gain(channel);
	108	DEBUG(3, USRP_UHD, "Tx get gain = "<<gain);
	109	}
	110	else{
	111
	112	}
	113
92	114	}
93	115
94	116	void USRP_UHD_TX_Control_i::get_frequency_range(CORBA::ULong channel, CORBA::Float &fmin, CORBA::Float &fmax, CORBA::Float &fstep)
95	117	{
96
97
98		if (channel == 0) {
99		if (usrp_uhd->sdev) {
100		uhd::freq_range_t range = usrp_uhd->sdev->get_tx_freq_range();
101		// All values in range are in dB
102		fmin = range.start();
103		fmax = range.stop();
104		fstep = 0.0; // There is no step value in uhd::freq_range
105		}
106		} else {
107		return; ///\todo throw bad channel exception
108		}
	118	omni_mutex_lock l(usrp_uhd->tx_control_access);
	119
	120	if (usrp_uhd->sdev) {
	121	uhd::freq_range_t range = usrp_uhd->sdev->get_tx_freq_range(channel);
	122	// All values in range are in dB
	123	fmin = range.start();
	124	fmax = range.stop();
	125	fstep = range.step();
	126	DEBUG(3, USRP_UHD, "Tx Frequency range = "<<range.to_pp_string())
	127
	128	}
	129	else{
	130
	131	}
109	132
110	133	}
…	…
112	135	void USRP_UHD_TX_Control_i::set_frequency(CORBA::ULong channel, CORBA::Float f)
113	136	{
114		~~DEBUG(3, USRP_UHD, "In TX Control set frequency channel: " << channel << ", frequency: " << f~~);
115
116		if (~~channel == 0~~) {
117		uhd::tune_result_t result = usrp_uhd->sdev->set_tx_freq(f);
	137	omni_mutex_lock l(usrp_uhd->tx_control_access);
	138
	139	if (usrp_uhd->sdev) {
	140	uhd::tune_result_t result = usrp_uhd->sdev->set_tx_freq(f,channel);
118	141
119	142	DEBUG(3, USRP_UHD, "USRP_UHD TX tune_result:" <<std::endl<<
…	…
123	146	" \tActual_DSP_freq=" << result.actual_dsp_freq);
124	147	} else {
125		DEBUG(3, USRP_UHD, "USRP_UHD TX set_frequency (invalid channel)");
126		return;
	148
127	149	}
128	150
…	…
131	153	void USRP_UHD_TX_Control_i::get_frequency(CORBA::ULong channel, CORBA::Float &f)
132	154	{
133		f = usrp_uhd->sdev->get_tx_freq();
134		DEBUG(3, USRP_UHD, "In TX Control get frequency channel: " << channel << ", frequency: " << f);
135
	155	omni_mutex_lock l(usrp_uhd->tx_control_access);
	156	if(usrp_uhd->sdev){
	157	f = usrp_uhd->sdev->get_tx_freq(channel);
	158	}
	159	else{
	160
	161	}
136	162	}
137	163
…	…
157	183	{
158	184
159		DEBUG(3, USRP_UHD, "~~USRP_UHD TX setting~~ " << values.length() << " values, value[0].id " << values[0].id)
160		#if 0
	185	DEBUG(3, USRP_UHD, "TX set_values: " << values.length() << " values, value[0].id " << values[0].id)
	186
161	187	for (unsigned int i =0; i < values.length(); ++i) {
162	188	if (strcmp(values[i].id, "SET_MUX") == 0 ) {
…	…
169	195	CORBA::ULong atx;
170	196	values[i].value >>= atx;
171		DEBUG(3, USRP_UHD, "Set Auto TX/RX for ~~side~~ 1 to " << atx)
	197	DEBUG(3, USRP_UHD, "Set Auto TX/RX for DB1 to " << atx)
172	198	omni_mutex_lock l(usrp_uhd->tx_control_access);
173		if (usrp_uhd->tx_db0_control && usrp_uhd->rx_db0_control) {
174		if (atx) {
175		usrp_uhd->tx_db0_control->set_auto_tr(true);
176		usrp_uhd->rx_db0_control->set_auto_tr(true);
177		} else {
178		usrp_uhd->tx_db0_control->set_auto_tr(false);
179		usrp_uhd->rx_db0_control->set_auto_tr(false);
180		}
181		}
	199	usrp_uhd->sdev->get_tx_dboard_iface(0)->set_pin_ctrl(uhd::usrp::dboard_iface::UNIT_TX,atx,0x0);
	200	usrp_uhd->sdev->get_tx_dboard_iface(0)->set_pin_ctrl(uhd::usrp::dboard_iface::UNIT_RX,atx,0x0);
	201	usrp_uhd->sdev->get_rx_dboard_iface(0)->set_pin_ctrl(uhd::usrp::dboard_iface::UNIT_TX,atx,0x0);
	202	usrp_uhd->sdev->get_rx_dboard_iface(0)->set_pin_ctrl(uhd::usrp::dboard_iface::UNIT_RX,atx,0x0);
	203
	204	} else if (strcmp(values[i].id, "SET_AUTO_TR_2") == 0) {
	205	CORBA::ULong atx;
	206	values[i].value >>= atx;
	207	DEBUG(3, USRP_UHD, "Set Auto TX/RX for DB2 to " << atx)
	208	omni_mutex_lock l(usrp_uhd->tx_control_access);
	209	usrp_uhd->sdev->get_tx_dboard_iface(1)->set_pin_ctrl(uhd::usrp::dboard_iface::UNIT_TX,atx,0x0);
	210	usrp_uhd->sdev->get_tx_dboard_iface(1)->set_pin_ctrl(uhd::usrp::dboard_iface::UNIT_RX,atx,0x0);
	211	usrp_uhd->sdev->get_rx_dboard_iface(1)->set_pin_ctrl(uhd::usrp::dboard_iface::UNIT_TX,atx,0x0);
	212	usrp_uhd->sdev->get_rx_dboard_iface(1)->set_pin_ctrl(uhd::usrp::dboard_iface::UNIT_RX,atx,0x0);
	213
182	214	}
183	215	}
184		#endif
	216
185	217	}
186	218
…	…
189	221	omni_mutex_lock l(usrp_uhd->tx_control_access);
190	222	///\TODO: rate matching in UHD works a little different. Review
191		double master_clock = usrp_uhd->sdev->get_master_clock_rate();
192		double request_da_rate = master_clock/(double)I;
193		usrp_uhd->sdev->set_tx_rate(request_da_rate,channel);
194		double real_da_rate = usrp_uhd->sdev->get_tx_rate(channel);
195		DEBUG(3, USRP_UHD, "Requested Tx sample rate ="<<request_da_rate<<", Real Tx sample rate ="<<real_da_rate)
	223	if(usrp_uhd->sdev){
	224	double master_clock = usrp_uhd->sdev->get_master_clock_rate();
	225	double request_da_rate = master_clock/(double)I;
	226	usrp_uhd->sdev->set_tx_rate(request_da_rate,channel);
	227	double real_da_rate = usrp_uhd->sdev->get_tx_rate(channel);
	228	DEBUG(3, USRP_UHD, "Requested Tx sample rate ="<<request_da_rate<<", Real Tx sample rate ="<<real_da_rate)
	229	}
	230	else{
	231
	232	}
196	233	}
197	234
198	235	void USRP_UHD_TX_Control_i::get_interpolation_range(CORBA::ULong channel, CORBA::ULong &imin, CORBA::ULong &imax, CORBA::ULong &istep)
199	236	{
200		double master_clock = usrp_uhd->sdev->get_master_clock_rate();
201		uhd::meta_range_t tx_range = usrp_uhd->sdev->get_tx_rates(channel);
202		imax = master_clock/tx_range.start();
203		imin = master_clock/tx_range.stop();
204		istep = master_clock/tx_range.step();
205		DEBUG(3, USRP_UHD, "Interpolation min="<<imin<<", max="<<imax<<", step="<<istep)
	237	omni_mutex_lock l(usrp_uhd->tx_control_access);
	238	if(usrp_uhd->sdev){
	239	double master_clock = usrp_uhd->sdev->get_master_clock_rate();
	240	uhd::meta_range_t tx_range = usrp_uhd->sdev->get_tx_rates(channel);
	241	imax = master_clock/tx_range.start();
	242	imin = master_clock/tx_range.stop();
	243	istep = master_clocktx_range.step()/(tx_range.stop()tx_range.start());
	244	if(istep < 1)
	245	istep = 1;
	246	double step = master_clocktx_range.step()/(tx_range.stop()tx_range.start());
	247	DEBUG(3, USRP_UHD, "Interpolation min="<<imin<<", max="<<imax<<", step="<<istep)
	248	}
	249	else{
	250
	251	}
206	252	}
207	253
…	…
213	259	void USRP_UHD_RX_Control_i::set_number_of_channels(CORBA::ULong nchan)
214	260	{
215		DEBUG(1, USRP_UHD, "Request to set number of channels to " << nchan<<" not supported")
216
217		//omni_mutex_lock l(usrp_uhd->rx_control_access);
218
219		//usrp_uhd->usrp_uhd_ptr->set_nchannels(nchan);
	261	omni_mutex_lock l(usrp_uhd->rx_control_access);
	262	uhd::property_tree::sptr tree = usrp_uhd->dev->get_tree();
	263	uhd::fs_path db_path, mb_path = "/mboards";
	264
	265	int assigned_channel = 0;
	266	std::string subdev_spec;
	267	for(int i=0;(i<usrp_uhd->mb_count)&&(assigned_channel<nchan);i++){
	268	mb_path = "/mboards";
	269	mb_path = mb_path / tree->list("/mboards")[i];
	270
	271	for(int j=0;(j<usrp_uhd->db_count)&&(assigned_channel<nchan);j++){
	272	db_path = mb_path / "dboards" / tree->list( mb_path / "dboards")[j];
	273	uhd::usrp::dboard_eeprom_t prom = tree->access<uhd::usrp::dboard_eeprom_t>(db_path / "rx_eeprom").get();
	274	if (prom.id != uhd::usrp::dboard_id_t::none()){
	275	subdev_spec = subdev_spec + tree->list( mb_path / "dboards")[j] + ":"
	276	+ tree->list(db_path / "rx_frontends").at(0) + " ";
	277	assigned_channel++;
	278
	279	}
	280
	281
	282	}
	283	DEBUG(3, USRP_UHD, "subdev of rx channel@MB"<<i<<" = "<<subdev_spec)
	284	usrp_uhd->sdev->set_rx_subdev_spec(uhd::usrp::subdev_spec_t(subdev_spec),i);
	285
	286	}
	287	usrp_uhd->rx_channels = usrp_uhd->sdev->get_rx_num_channels();
	288	DEBUG(3, USRP_UHD, "# of Rx Channels Requested="<<nchan<<", Real="<<usrp_uhd->rx_channels)
220	289	}
221	290
222	291	void USRP_UHD_RX_Control_i::get_number_of_channels(CORBA::ULong &num)
223	292	{
224		DEBUG(1, USRP_UHD, "Request to get number of channels not supported")
225		//omni_mutex_lock l(usrp_uhd->rx_control_access);
226
227		//num = usrp_uhd->usrp_uhd_ptr->nchannels();
	293	omni_mutex_lock l(usrp_uhd->rx_control_access);
	294	num = usrp_uhd->sdev->get_rx_num_channels();
	295	DEBUG(3, USRP_UHD, "Rx get number of channels = "<<num)
228	296	}
229	297
…	…
233	301
234	302	if (channel == 0 && usrp_uhd->sdev) {
235		uhd::gain_range_t range = usrp_uhd->sdev->get_rx_gain_range();
	303	uhd::gain_range_t range = usrp_uhd->sdev->get_rx_gain_range(channel);
236	304	// All values in range are in dB
237	305	gmin = range.start();
…	…
243	311	void USRP_UHD_RX_Control_i::set_gain(CORBA::ULong channel, CORBA::Float gain)
244	312	{
245		DEBUG(1, USRP_UHD, "set gain to "<<gain);
246
247		omni_mutex_lock l(usrp_uhd->rx_control_access);
248
249		if (channel == 0) {
250		if (usrp_uhd->sdev)
251		usrp_uhd->sdev->set_rx_gain(gain);
	313	omni_mutex_lock l(usrp_uhd->rx_control_access);
	314
	315	if (usrp_uhd->sdev) {
	316	usrp_uhd->sdev->set_rx_gain(gain,channel);
	317	DEBUG(3, USRP_UHD, "Rx set gain = "<<gain)
	318	}
	319	else {
	320
	321	}
	322	}
	323
	324	void USRP_UHD_RX_Control_i::get_gain(CORBA::ULong channel, CORBA::Float &gain)
	325	{
	326	omni_mutex_lock l(usrp_uhd->rx_control_access);
	327	if (usrp_uhd->sdev) {
	328	gain = usrp_uhd->sdev->get_rx_gain(channel);
	329	DEBUG(3, USRP_UHD, "Rx get gain = "<<gain);
	330	}
	331	else{
	332
	333	}
	334	}
	335
	336	void USRP_UHD_RX_Control_i::get_frequency_range(CORBA::ULong channel, CORBA::Float &fmin, CORBA::Float &fmax, CORBA::Float &fstep)
	337	{
	338	omni_mutex_lock l(usrp_uhd->rx_control_access);
	339
	340	if (usrp_uhd->sdev) {
	341	uhd::freq_range_t range = usrp_uhd->sdev->get_rx_freq_range(channel);
	342	// All values in range are in dB
	343	fmin = range.start();
	344	fmax = range.stop();
	345	fstep = range.step();
	346	DEBUG(3, USRP_UHD, "Rx Frequency range = "<<range.to_pp_string())
	347
	348	}
	349	else{
	350
	351	}
	352	}
	353
	354	void USRP_UHD_RX_Control_i::set_frequency(CORBA::ULong channel, CORBA::Float f)
	355	{
	356	omni_mutex_lock l(usrp_uhd->rx_control_access);
	357
	358	if (usrp_uhd->sdev) {
	359	uhd::tune_result_t result = usrp_uhd->sdev->set_rx_freq(f,channel);
	360
	361	DEBUG(3, USRP_UHD, "USRP_UHD RX tune_result:" <<std::endl<<
	362	" \tTarget_RF_Freq=" << result.target_rf_freq <<std::endl<<
	363	" \tActual_RF_Freq=" << result.actual_rf_freq <<std::endl<<
	364	" \tTarget_DSP_freq=" << result.target_dsp_freq <<std::endl<<
	365	" \tActual_DSP_freq=" << result.actual_dsp_freq);
252	366	} else {
253		DEBUG(1, USRP_UHD, "Attempt to set gain on non-existent db.");
254		return; ///\todo throw bad channel exception
255		}
256		}
257
258		void USRP_UHD_RX_Control_i::get_gain(CORBA::ULong channel, CORBA::Float &gain)
259		{
260		omni_mutex_lock l(usrp_uhd->rx_control_access);
261		if (channel == 0 && usrp_uhd->sdev)
262		gain = usrp_uhd->sdev->get_rx_gain();
263		else
264		return; ///\todo throw bad channel exception
265		}
266
267		void USRP_UHD_RX_Control_i::get_frequency_range(CORBA::ULong channel, CORBA::Float &fmin, CORBA::Float &fmax, CORBA::Float &fstep)
268		{
269		omni_mutex_lock l(usrp_uhd->rx_control_access);
270
271		if (channel == 0) {
272		if (usrp_uhd->sdev) {
273		uhd::freq_range_t range = usrp_uhd->sdev->get_rx_freq_range();
274		// All values in range are in dB
275		fmin = range.start();
276		fmax = range.stop();
277		fstep = 0.0; // There is no step value in uhd::freq_range
278		}
279		} else {
280		return; ///\todo throw bad channel exception
281		}
282		}
283
284		void USRP_UHD_RX_Control_i::set_frequency(CORBA::ULong channel, CORBA::Float f)
285		{
286		DEBUG(3, USRP_UHD, "In RX Control set frequency channel: " << channel << ", frequency: " << f);
287
288		omni_mutex_lock l(usrp_uhd->rx_control_access);
289
290		if (channel == 0) {
291		uhd::tune_result_t result = usrp_uhd->sdev->set_rx_freq(f);
292		/*
293		DEBUG(3, USRP_UHD, "USRP_UHD RX tune_result:" <<
294		" target_inter_freq=" << result.target_inter_freq <<
295		" actual_inter_freq=" << result.actual_inter_freq <<
296		" target_dsp_freq=" << result.target_dsp_freq <<
297		" actual_dsp_freq=" << result.actual_dsp_freq);
298		*/
299		} else {
300		DEBUG(3, USRP_UHD, "USRP_UHD TX set_frequency (invalid channel)");
301		return;
	367
302	368	}
303	369	}
…	…
305	371	void USRP_UHD_RX_Control_i::get_frequency(CORBA::ULong channel, CORBA::Float &f)
306	372	{
307		DEBUG(1, USRP_UHD, "RX get_frequency not supported!!");
308
309		f = 0.0;
	373	omni_mutex_lock l(usrp_uhd->rx_control_access);
	374	if(usrp_uhd->sdev){
	375	f = usrp_uhd->sdev->get_rx_freq(channel);
	376	}
	377	else{
	378
	379	}
310	380	}
311	381
…	…
326	396	omni_mutex_lock l(usrp_uhd->rx_control_access);
327	397	DEBUG(0, USRP_UHD, "USRP_RX_Control stop Called")
328
329		usrp_uhd->rx_active = false;//false;
	398	usrp_uhd->rx_active = false;
330	399	}
331	400
332	401	void USRP_UHD_RX_Control_i::set_values(const CF::Properties &values)
333	402	{
334		~~/* DEBUG(3, USRP_UHD, "USRP_UHD RX setting~~ " << values.length() << " values, value[0].id " << values[0].id)
	403	DEBUG(3, USRP_UHD, "RX set_values: " << values.length() << " values, value[0].id " << values[0].id)
335	404
336	405	for (unsigned int i =0; i < values.length(); ++i) {
…	…
349	418	CORBA::ULong ant;
350	419	values[i].value >>= ant;
351		~~DEBUG(3, USRP_UHD, "Setting receive antenna to " << ant)~~
352	420	omni_mutex_lock l(usrp_uhd->rx_control_access);
353		if (usrp_uhd->rx_db0_control)
354		usrp_uhd->rx_db0_control->select_rx_antenna(ant);
	421	std::vector<std::string>rx_antennas0 = usrp_uhd->sdev->get_rx_antennas(0);
	422	DEBUG(3, USRP_UHD, "Setting receive antenna to " << rx_antennas0[ant])
	423
	424	usrp_uhd->sdev->set_rx_antenna(rx_antennas0[ant]);
	425
	426	} else if (strcmp(values[i].id, "SET_RX_ANT_2") == 0 ) {
	427	CORBA::ULong ant;
	428	values[i].value >>= ant;
	429	omni_mutex_lock l(usrp_uhd->rx_control_access);
	430	std::vector<std::string>rx_antennas1 = usrp_uhd->sdev->get_rx_antennas(1);
	431	DEBUG(3, USRP_UHD, "Setting receive antenna to " << rx_antennas1[ant])
	432	usrp_uhd->sdev->set_rx_antenna(rx_antennas1[ant]);
	433
355	434	}
356		}*/
	435	}
357	436	}
358	437
…	…
360	439	{
361	440	omni_mutex_lock l(usrp_uhd->rx_control_access);
362		if(channel == 0 && usrp_uhd->sdev)
363		usrp_uhd->sdev->set_rx_rate(ADC_RATE/D);
	441	///\TODO: rate matching in UHD works a little different. Review
	442	double master_clock = usrp_uhd->sdev->get_master_clock_rate();
	443	double request_da_rate = master_clock/(double)D;
	444	usrp_uhd->sdev->set_rx_rate(request_da_rate,channel);
	445	double real_da_rate = usrp_uhd->sdev->get_rx_rate(channel);
	446	DEBUG(3, USRP_UHD, "Requested Rx sample rate ="<<request_da_rate<<", Real Rx sample rate ="<<real_da_rate)
364	447	}
365	448
366	449	void USRP_UHD_RX_Control_i::get_decimation_range(CORBA::ULong channel, CORBA::ULong &dmin, CORBA::ULong &dmax, CORBA::ULong &dstep)
367	450	{
368		DEBUG(1, USRP_UHD, "get_decimation_rate not supported!!")
369		dmin = 0;
370		dmax = 0;
371		dstep = 0;
	451	omni_mutex_lock l(usrp_uhd->rx_control_access);
	452	if(usrp_uhd->sdev){
	453	double master_clock = usrp_uhd->sdev->get_master_clock_rate();
	454	uhd::meta_range_t rx_range = usrp_uhd->sdev->get_rx_rates(channel);
	455	dmax = master_clock/rx_range.start();
	456	dmin = master_clock/rx_range.stop();
	457	dstep = master_clockrx_range.step()/(rx_range.stop()rx_range.start());
	458	if(dstep < 1)
	459	dstep = 1;
	460
	461	DEBUG(3, USRP_UHD, "Decimation min="<<dmin<<", max="<<dmax<<", step="<<dstep)
	462	}
	463	else{
	464
	465	}
372	466	}
373	467
…	…
375	469	{
376	470	omni_mutex_lock l(usrp_uhd->rx_control_access);
377
378	471	usrp_uhd->rx_packet_size = N;
379	472	}

ossiedev/branches/june/trunk/platform/USRP_UHD/xml/USRP_UHD.scd.xml

r10608	r11094
17	17	<supportsinterface repid="IDL:CF/TestableObject:1.0" supportsname="TestableObject" />
18	18	<ports>
19		<provides repid="IDL:standardInterfaces/TX_Control:1.0" providesname="U2_TX_Control">
	19	<provides repid="IDL:standardInterfaces/TX_Control:1.0" providesname="UHD_TX_Control">
20	20	<porttype type="control" />
21	21	</provides>
22		<provides repid="IDL:standardInterfaces/RX_Control:1.0" providesname="U2_RX_Control">
	22	<provides repid="IDL:standardInterfaces/RX_Control:1.0" providesname="UHD_RX_Control">
23	23	<porttype type="control" />
24	24	</provides>
25		<provides repid="IDL:standardInterfaces/complexShort:1.0" providesname="U~~2_TX_Data~~">
	25	<provides repid="IDL:standardInterfaces/complexShort:1.0" providesname="UHD_TX_Data_1">
26	26	<porttype type="data" />
27	27	</provides>
28		<uses repid="IDL:standardInterfaces/complexShort:1.0" usesname="U2_RX_Data_1">
	28	<provides repid="IDL:standardInterfaces/complexShort:1.0" providesname="UHD_TX_Data_2">
	29	<porttype type="data" />
	30	</provides>
	31	<uses repid="IDL:standardInterfaces/complexShort:1.0" usesname="UHD_RX_Data_1">
29	32	<porttype type="data" />
30	33	</uses>
31		<uses repid="IDL:standardInterfaces/complexShort:1.0" usesname="U2_RX_Data_2">
	34	<uses repid="IDL:standardInterfaces/complexShort:1.0" usesname="UHD_RX_Data_2">
32	35	<porttype type="data" />
33	36	</uses>
…	…
48	51	<inheritsinterface repid="IDL:CF/TestableObject:1.0" />
49	52	</interface>
50		<interface repid="IDL:standardInterfaces/TX_Control:1.0" name="U2_TX_Control" />
51		<interface repid="IDL:standardInterfaces/RX_Control:1.0" name="U2_RX_Control" />
	53	<interface repid="IDL:standardInterfaces/TX_Control:1.0" name="UHD_TX_Control" />
	54	<interface repid="IDL:standardInterfaces/RX_Control:1.0" name="UHD_RX_Control" />
52	55	</interfaces>
53	56	</softwarecomponent>

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