| | 142 | |
| | 143 | |
| | 144 | |
| | 145 | |
| | 146 | |
| | 147 | |
| | 148 | def writePortDecl(output,comp): |
| | 149 | """ This function writes the corba declarations of the ports to the init method""" |
| | 150 | |
| | 151 | #TODO: test this method |
| | 152 | inCount = 0 |
| | 153 | for p in c.ports: |
| | 154 | if p.type == "Provides": |
| | 155 | ts = " "*8 + "self.inPort" + inCount + '_servant = dataIn_complexShort_i(self, "' + p.name + '")\n' |
| | 156 | ts = ts + " "*8 + 'self.inPort' + inCount + '_var = self.inPort' + inCount + '_servant._this()\n\n' |
| | 157 | output.write(ts) |
| | 158 | inCount += 1 |
| | 159 | |
| | 160 | outCount = 0 |
| | 161 | for p in c.ports: |
| | 162 | if p.type == "Uses": |
| | 163 | ts = " "*8 + 'self.outPort' + outCount + '_servant = dataOut_' + p.interface + '_i(self, "' + p.name + '")\n' |
| | 164 | ts = ts + " "*8 + 'self.outPort' + outCount + '_var = self.outPort' + outCount + '_servant._this()\n' |
| | 165 | ts = ts + " "*8 + 'self.outPort' + outCount + '_active = False\n\n' |
| | 166 | output.write(ts) |
| | 167 | outCount += 1 |
| | 168 | |
| | 169 | |
| 141 | | for line in inputH.readlines(): |
| 142 | | l_out = line.replace("__CLASS_DEF__",comp.name.upper()+"_IMPL_H") |
| 143 | | l_out = l_out.replace("__Class_name__",comp.name+"_i") |
| 144 | | if l_out.find("__PORT_DECL__") != -1: |
| 145 | | self.writePortDecl(outputH,comp) |
| 146 | | continue |
| 147 | | if l_out.find("__ACE_INCLUDES__") != -1: |
| 148 | | if comp.ace == True: |
| 149 | | l_out = '#include "ace/Task.h"\n' |
| 150 | | else: |
| 151 | | continue |
| 152 | | if l_out.find("__ACE_INHERIT__") != -1: |
| 153 | | if comp.ace == True: |
| 154 | | l_out = l_out.replace("__ACE_INHERIT__",", public ACE_Task<ACE_MT_SYNCH>") |
| 155 | | else: |
| 156 | | l_out = l_out.replace("__ACE_INHERIT__","") |
| 157 | | if l_out.find("__ACE_SVC_DECL__") != -1: |
| 158 | | if comp.ace == True: |
| 159 | | l_out = l_out.replace("__ACE_SVC_DECL__",'int svc(void);\n size_t queue_size;') |
| 160 | | else: |
| 161 | | continue |
| 162 | | if l_out.find("__FRIEND_DECL__") != -1: |
| 163 | | l_out = l_out.replace("__FRIEND_DECL__","") |
| 164 | | self.writeFriendDecl(outputH,comp) |
| 165 | | continue |
| 166 | | |
| 167 | | outputH.write(l_out) |
| 168 | | |
| 169 | | inputH.close() |
| 170 | | outputH.close() |
| 171 | | |
| | 173 | |
| 189 | | if l_out.find("__ACE_SVC_PORTS__") != -1: |
| 190 | | self.writeACESvcPorts(outputCPP,comp) |
| 191 | | continue |
| 192 | | if l_out.find("__ACE_SVC_DEF__") != -1: |
| 193 | | if comp.ace == True: |
| 194 | | self.writeACESvcDef(outputCPP,comp,'component',comp.timing, comp) |
| 195 | | continue |
| 196 | | outputCPP.write(l_out) |
| 197 | | |
| 198 | | inputCPP.close() |
| 199 | | outputCPP.close() |
| 200 | | |
| 201 | | # generate the main.cpp files for each component |
| 202 | | inputMain = open('generate/templates/custom_ports/sampleMain.cpp','r') |
| 203 | | outputMain = open(self.path + comp.name + "/main.cpp",'w') |
| 204 | | self.addGPL(outputMain,comp.name) |
| 205 | | |
| 206 | | for line in inputMain.readlines(): |
| 207 | | l_out = line.replace("__IncludeFile__",comp.name) |
| 208 | | l_out = l_out.replace("__Class_name__",comp.name+"_i") |
| 209 | | l_out = l_out.replace("__CLASS_VAR__",comp.name.lower()) |
| 210 | | if l_out.find("__CLASS_VAR_ACE__") != -1: |
| 211 | | if comp.ace == True: |
| 212 | | l_out = l_out.replace("__CLASS_VAR_ACE__",comp.name.lower()) |
| 213 | | else: |
| 214 | | continue |
| 215 | | if l_out.find("__NAME_SPACE__") != -1: |
| 216 | | ns_list = [] |
| 217 | | for p in comp.ports: |
| 218 | | if p.interface.nameSpace not in ns_list: |
| 219 | | ns_list.append(p.interface.nameSpace) |
| 220 | | l_out = '' |
| 221 | | for tmpns in ns_list: |
| 222 | | l_out += 'using namespace ' + tmpns + ';\n' |
| 223 | | |
| 224 | | outputMain.write(l_out) |
| 225 | | |
| 226 | | inputMain.close() |
| 227 | | outputMain.close() |
| | 185 | |