Changeset 8206
- Timestamp:
- 08/26/08 13:10:14 (5 years ago)
- Files:
-
- 1 modified
-
ossiedev/branches/mcarrick/VHDL/reg/reg.vhd (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
ossiedev/branches/mcarrick/VHDL/reg/reg.vhd
r8203 r8206 1 1 -- Register implementation 2 2 -- 3 -- Acts as a single delay. When a value is passed in, it is 4 -- held for a clock period before appearing on the output. 5 -- Resetting the circuit sets the held value and the output 6 -- to zero. 3 -- The circuit is a simple D flip flop implementation. 7 4 -- 8 5 -- The circuit is scalable to the number of bits the register … … 28 25 architecture register_behav of reg is 29 26 30 signal reg : std_logic_vector(numBits-1 downto 0);31 32 27 begin 33 28 process(clock) … … 36 31 if (chipEnable = '1') then -- only activate circuit when chip enable'd 37 32 if (reset = '1') then 38 reg <= (others => '0'); -- reset register value to zero39 33 dataOut <= (others => '0'); -- reset output value to zero 40 34 elsif (reset = '0') then 41 dataOut <= reg; 42 reg <= dataIn; 35 dataOut <= dataIn; 43 36 end if; 44 37 end if; … … 52 45 53 46 47
