Changeset 8218
- Timestamp:
- 08/27/08 13:03:39 (5 years ago)
- Files:
-
- 1 modified
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ossiedev/branches/mcarrick/VHDL/reg/reg_tb.vhd (modified) (5 diffs)
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ossiedev/branches/mcarrick/VHDL/reg/reg_tb.vhd
r8203 r8218 3 3 library ieee; 4 4 use ieee.std_logic_1164.all; 5 use ieee.numeric_std.all; 5 6 6 7 entity reg_tb is … … 22 23 end component reg; 23 24 24 25 signal DATA IN, DATAOUT : std_logic_vector(3 downto 0);25 signal DATAIN : std_logic_vector(3 downto 0) := (others => '0'); 26 signal DATAOUT : std_logic_vector(3 downto 0); 26 27 signal CHIPENABLE, RESET : std_logic; 27 28 signal CLOCK : std_logic := '0'; … … 41 42 ); 42 43 43 44 45 44 run_clock : process 46 45 begin … … 50 49 51 50 enter_inputs : process 51 variable errors : boolean; 52 52 53 begin 53 -- test inputs 54 wait for 10 ns; 54 55 -- reset chip, set enable 56 RESET <= '1'; 55 57 CHIPENABLE <= '1'; 58 wait for 30 ns; 59 56 60 RESET <= '0'; 57 DATAIN <= x"0";58 61 59 wait for 20 ns; 60 DATAIN <= x"1"; 61 62 wait for 20 ns; 63 DATAIN <= x"2"; 64 65 wait for 20 ns; 66 DATAIN <= x"3"; 62 for i in 0 to 15 loop 67 63 68 -- test the chip enable 69 wait for 20 ns; 70 CHIPENABLE <= '0'; 64 DATAIN <= std_logic_vector(unsigned(DATAIN) + 1); 65 wait for 20 ns; 71 66 72 wait for 20 ns; 73 DATAIN <= x"4"; 74 75 wait for 20 ns; 76 DATAIN <= x"5"; 77 78 wait for 20 ns; 79 DATAIN <= x"6"; 80 81 -- test the reset 82 wait for 20 ns; 83 RESET <= '1'; 84 DATAIN <= x"7"; 85 86 wait for 20 ns; 87 DATAIN <= x"8"; 88 89 wait for 20 ns; 90 CHIPENABLE <= '1'; 91 RESET <= '1'; 92 DATAIN <= x"9"; 93 94 wait for 20 ns; 95 RESET <= '0'; 96 DATAIN <= x"A"; 97 98 wait for 20 ns; 99 DATAIN <= x"B"; 67 if (DATAIN /= DATAOUT) then 68 report "DATAIN does not equal DATAOUT"; 69 end if; 70 71 end loop; 72 73 assert errors 74 report "Test failed." 75 severity error; 76 assert not(errors) 77 report "Test Passed." 78 severity note; 79 80 wait; 100 81 101 82 end process enter_inputs; … … 106 87 107 88 89
