Changeset 8221
- Timestamp:
- 08/27/08 15:33:30 (5 years ago)
- Files:
-
- 1 modified
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- Unmodified
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ossiedev/branches/mcarrick/VHDL/full_adder/full_adder_tb.vhd
r8211 r8221 3 3 library ieee; 4 4 use ieee.std_logic_1164.all; 5 use ieee.numeric_std.all; 5 6 6 7 entity test_fa is … … 30 31 ); 31 32 33 enter_inputs : process 32 34 33 set_inputs : process34 35 begin 36 35 37 A <= '0'; 36 38 B <= '0'; 37 39 CIN <= '0'; 38 40 wait for 1 ns; 41 if (S /= '0' or COUT /= '0') then 42 report "Bad Calculation! Should be: S = 0, COUT = 0."; 43 end if; 39 44 wait for 5 ns; 45 40 46 A <= '0'; 41 47 B <= '0'; 42 48 CIN <= '1'; 49 wait for 1 ns; 50 if (S /= '1' or COUT /= '0') then 51 report "S and COUT calculated incorrectly."; 52 end if; 53 wait for 5 ns; 43 54 44 wait for 5 ns;45 55 A <= '0'; 46 56 B <= '1'; 47 57 CIN <= '0'; 58 wait for 1 ns; 59 if (S /= '1' or COUT /= '0') then 60 report "S and COUT calculated incorrectly."; 61 end if; 62 wait for 5 ns; 48 63 49 wait for 5 ns;50 64 A <= '0'; 51 65 B <= '1'; 52 66 CIN <= '1'; 67 wait for 1 ns; 68 if (S /= '0' or COUT /= '1') then 69 report "S and COUT calculated incorrectly."; 70 end if; 71 wait for 5 ns; 53 72 54 wait for 5 ns;55 73 A <= '1'; 56 74 B <= '0'; 57 75 CIN <= '0'; 76 wait for 1 ns; 77 if (S /= '1' or COUT /= '0') then 78 report "S and COUT calculated incorrectly."; 79 end if; 80 wait for 5 ns; 58 81 59 wait for 5 ns;60 82 A <= '1'; 61 83 B <= '0'; 62 84 CIN <= '1'; 85 wait for 1 ns; 86 if (S /= '0' or COUT /= '1') then 87 report "S and COUT calculated incorrectly."; 88 end if; 89 wait for 5 ns; 63 90 64 wait for 5 ns;65 91 A <= '1'; 66 92 B <= '1'; 67 93 CIN <= '0'; 94 wait for 1 ns; 95 if (S /= '0' or COUT /= '1') then 96 report "S and COUT calculated incorrectly."; 97 end if; 98 wait for 5 ns; 68 99 69 wait for 5 ns;70 100 A <= '1'; 71 101 B <= '1'; 72 102 CIN <= '1'; 103 wait for 1 ns; 104 if (S /= '1' or COUT /= '1') then 105 report "S and COUT calculated incorrectly."; 106 end if; 107 wait for 5 ns; 108 109 wait; 73 110 74 wait for 5 ns; 111 end process enter_inputs; 112 113 end architecture test_fa_tb; 75 114 76 115 77 end process set_inputs;78 79 80 81 82 83 84 end architecture test_fa_tb;
