Changeset 8225 for ossiedev/branches/mcarrick/VHDL/carry_lookahead_adder/carry_lookahead_adder_tb.vhd

Timestamp:

08/28/08 14:15:18 (5 years ago)

Author:

mcarrick

Message:

added automated testing

Files:

• ossiedev/branches/mcarrick/VHDL/carry_lookahead_adder/carry_lookahead_adder_tb.vhd (modified) (4 diffs)

ossiedev/branches/mcarrick/VHDL/carry_lookahead_adder/carry_lookahead_adder_tb.vhd

@@ -3 +3 @@
 library ieee;
 use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 
 entity test_CLA is
@@ -20 +21 @@
         end component carry_lookahead_adder;
         
-        signal A, B, S : std_logic_vector(3 downto 0);
+        signal A, B : std_logic_vector(3 downto 0) := (others => '0');
+        signal S : std_logic_vector(3 downto 0);
         signal CIN, COUT : std_logic;
-        
+
+        signal result : std_logic_vector(4 downto 0);
+        signal check : std_logic_vector(4 downto 0);
+
         begin
 
@@ -35 +40 @@
                         );
 
+                -- calculate 5 bit result from circuit
+                result <= COUT & S;
+                -- calculate 5 bit result independently
+                check <= std_logic_vector(unsigned("0" & A) + unsigned("0" & B) + ("000" & CIN));
+
                 enter_inputs : process
                 begin
 
-                        A <= x"0";
-                        B <= x"0";
-                        CIN <= '0';
+                        -- loop for CIN
+                        for i in 0 to 1 loop
 
-                        wait for 5 ns;
-                        A <= x"0";
-                        B <= x"1";
-                        CIN <= '1';
+                                -- set CIN test values
+                                if (i = 0) then
+                                        CIN <= '0';
+                                else
+                                        CIN <= '1';
+                                end if;
+                        
+                                -- loop for A
+                                for iA in 0 to 15 loop
 
-                        wait for 5 ns;
-                        A <= x"2";
-                        B <= x"2";
-                        CIN <= '0';
+                                        if (iA = 0) then
+                                                A <= (others => '0');
+                                        elsif (iA > 0) then
+                                                A <= std_logic_vector(unsigned(A) + 1);
+                                        end if;
 
-                        wait for 5 ns;
-                        A <= x"F";
-                        B <= x"1";
-                        CIN <= '0';
+                                        -- loop for B
+                                        for iB in 0 to 15 loop
+                                        
+                                                if (iB = 0) then
+                                                        B <= (others => '0');
+                                                elsif (iB > 0) then
+                                                        B <= std_logic_vector(unsigned(B) + 1);
+                                                end if;
 
-                        wait for 5 ns;
-                        A <= x"F";
-                        B <= x"F";
-                        CIN <= '1';
+                                                wait for 1 ns;
 
-                        wait for 5 ns;
-                        A <= x"A";
-                        B <= x"5";
-                        CIN <= '1';
+                                                if (check /= result) then
+                                                        report "The summation has been calculated incorrectly!";
+                                                end if;
 
-                        wait for 5 ns;
+                                        end loop;
+
+                                end loop;
+
+                        end loop;
 
                 end process enter_inputs;
@@ -74 +93 @@
 
 
-        
 
+