Changeset 8236
- Timestamp:
- 08/28/08 21:13:11 (5 years ago)
- Location:
- ossiedev/branches/mcarrick/VHDL/carry_lookahead_adder
- Files:
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- 4 modified
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carry_lookahead_adder.vhd (modified) (9 diffs)
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carry_lookahead_adder_logic.vhd (modified) (3 diffs)
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carry_lookahead_adder_tb.vhd (modified) (4 diffs)
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carry_lookahead_logic_tb.vhd (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
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ossiedev/branches/mcarrick/VHDL/carry_lookahead_adder/carry_lookahead_adder.vhd
r8216 r8236 13 13 use ieee.std_logic_1164.all; 14 14 15 entity carry _lookahead_adder is15 entity carryLookAheadAdder is 16 16 generic ( numBits : integer := 4 17 17 ); … … 22 22 cOut : out std_logic 23 23 ); 24 end entity carry _lookahead_adder;24 end entity carryLookAheadAdder; 25 25 26 architecture carry _lookahead_adder_struc of carry_lookahead_adder is26 architecture carryLookAheadAdderStruc of carryLookAheadAdder is 27 27 28 28 -- full adder (with p&g functions) component 29 component full _adder_pgis29 component fullAdderPG is 30 30 port ( a : in std_logic; 31 31 b : in std_logic; … … 35 35 g : out std_logic 36 36 ); 37 end component full _adder_pg;37 end component fullAdderPG; 38 38 39 39 -- logic to determine carries given p&g values 40 component carry _lookahead_logic is40 component carryLookAheadLogic is 41 41 generic ( numBits : integer := 4 42 42 ); … … 46 46 c : out std_logic_vector(numBits-1 downto 0) 47 47 ); 48 end component carry _lookahead_logic;48 end component carryLookAheadLogic; 49 49 50 50 -- carry value … … 62 62 63 63 -- case for first adder 64 first_adder : full _adder_pg64 first_adder : fullAdderPG 65 65 port map ( a => a(0), 66 66 b => b(0), … … 76 76 chain_adders : for i in 1 to numBits-2 generate 77 77 78 middle_adders : full _adder_pg78 middle_adders : fullAdderPG 79 79 port map ( a => a(i), 80 80 b => b(i), … … 90 90 91 91 -- case for last adder 92 last_adder : full _adder_pg92 last_adder : fullAdderPG 93 93 port map ( a => a(numBits-1), 94 94 b => b(numBits-1), … … 100 100 101 101 -- CLA p&g logic 102 CLA_logic : carry _lookahead_logic102 CLA_logic : carryLookAheadLogic 103 103 generic map ( numBits => numBits 104 104 ) … … 114 114 end generate valid_numBits; 115 115 116 end architecture carry _lookahead_adder_struc;116 end architecture carryLookAheadAdderStruc; 117 117 118 118 119 119 120 -
ossiedev/branches/mcarrick/VHDL/carry_lookahead_adder/carry_lookahead_adder_logic.vhd
r8216 r8236 5 5 -- for the number of bits is 2. 6 6 -- 7 -- This component requires the carryLookAheadLogic 8 -- component which computes all of the propagate and 9 -- generate functions. 7 10 8 11 library ieee; 9 12 use ieee.std_logic_1164.all; 10 13 11 entity carry _lookahead_logic is14 entity carryLookAheadLogic is 12 15 generic ( numBits : integer := 4 13 16 ); … … 17 20 c : out std_logic_vector(numBits-1 downto 0) 18 21 ); 19 end entity carry _lookahead_logic;22 end entity carryLookAheadLogic; 20 23 21 architecture carry _lookahead_logic_behav of carry_lookahead_logic is24 architecture carryLookAheadLogicBehav of carryLookAheadLogic is 22 25 23 26 -- internal signal for carry values … … 51 54 c <= carry; 52 55 53 54 55 end architecture carry_lookahead_logic_behav; 56 end architecture carryLookAheadLogicBehav; 56 57 57 58 58 59 59 60 61 -
ossiedev/branches/mcarrick/VHDL/carry_lookahead_adder/carry_lookahead_adder_tb.vhd
r8225 r8236 10 10 architecture test_CLA_tb of test_CLA is 11 11 12 component carry _lookahead_adder is12 component carryLookAheadAdder is 13 13 generic ( numBits : integer := 4 14 14 ); … … 19 19 cOut : out std_logic 20 20 ); 21 end component carry _lookahead_adder;21 end component carryLookAheadAdder; 22 22 23 23 signal A, B : std_logic_vector(3 downto 0) := (others => '0'); … … 30 30 begin 31 31 32 CLA_inst : carry _lookahead_adder32 CLA_inst : carryLookAheadAdder 33 33 generic map ( numBits => 4 34 34 ) … … 95 95 96 96 97 98 -
ossiedev/branches/mcarrick/VHDL/carry_lookahead_adder/carry_lookahead_logic_tb.vhd
r8216 r8236 9 9 architecture test_cla_logic_tb of test_cla_logic is 10 10 11 component carry _lookahead_logic is11 component carryLookAheadLogic is 12 12 generic ( numBits : integer := 4 13 13 ); … … 17 17 c : out std_logic_vector(numBits-1 downto 0) 18 18 ); 19 end component carry_lookahead_logic; 20 19 end component carryLookAheadLogic; 21 20 22 21 signal P, G, C : std_logic_vector(3 downto 0); … … 25 24 begin 26 25 27 cla_logic_inst : carry _lookahead_logic26 cla_logic_inst : carryLookAheadLogic 28 27 generic map ( numBits => 4 29 28 ) … … 69 68 end process enter_inputs; 70 69 71 72 70 end architecture test_cla_logic_tb; 73 71 74 72 75 73 74
