Changeset 8606
- Timestamp:
- 01/28/09 21:48:06 (4 years ago)
- Location:
- ossiedev/branches/ttsou/dist/platform/USRP
- Files:
-
- 5 added
- 12 removed
- 7 modified
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Makefile.am (modified) (1 diff)
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config (added)
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config/aclocal.m4 (added)
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config/ax_boost_base.m4 (added)
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config/ax_boost_system.m4 (added)
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config/gr_lib64.m4 (added)
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configure.ac (modified) (1 diff)
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reconf (modified) (1 diff)
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src/USRP.cpp (modified) (15 diffs)
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src/USRP.h (modified) (9 diffs)
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src/basic.cpp (deleted)
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src/basic.h (deleted)
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src/db_base.cpp (deleted)
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src/db_base.h (deleted)
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src/dbsrx.cpp (deleted)
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src/dbsrx.h (deleted)
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src/flex.cpp (deleted)
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src/flex.h (deleted)
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src/lf.cpp (deleted)
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src/lf.h (deleted)
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src/main.cpp (modified) (4 diffs)
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src/port_impl.cpp (modified) (19 diffs)
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src/tvrx.cpp (deleted)
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src/tvrx.h (deleted)
Legend:
- Unmodified
- Added
- Removed
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ossiedev/branches/ttsou/dist/platform/USRP/Makefile.am
r5861 r8606 8 8 src/USRP.cpp \ 9 9 src/port_impl.cpp \ 10 src/USRP.h \ 11 src/db_base.h \ 12 src/db_base.cpp \ 13 src/flex.h \ 14 src/flex.cpp \ 15 src/basic.h \ 16 src/basic.cpp \ 17 src/dbsrx.h \ 18 src/dbsrx.cpp \ 19 src/tvrx.h \ 20 src/tvrx.cpp \ 21 src/lf.h \ 22 src/lf.cpp 10 src/USRP.h 23 11 24 12 ossieName = USRP -
ossiedev/branches/ttsou/dist/platform/USRP/configure.ac
r6343 r8606 15 15 16 16 AC_CHECK_LIB([omniORB4], [main], [], [AC_MSG_ERROR([cannot find omniORBi4 library])]) 17 AC_CHECK_LIB([omnithread], [main], [], [AC_MSG_ERROR([cannot find omnithread library])]) 17 18 AC_CHECK_LIB([omniDynamic4], [main], [], [AC_MSG_ERROR([cannot find omniDynamic4 library])]) 18 19 AC_CHECK_HEADERS([omniORB4/CORBA.h], [], [AC_MSG_ERROR([cannot find omniORB4 header files])]) 19 20 21 AX_BOOST_BASE([1.35]) 22 CPPFLAGS="$CPPFLAGS $BOOST_CPPFLAGS" 23 CFLAGS="$CFLAGS $BOOST_CPPFLAGS" 24 20 25 AC_CHECK_LIB([usrp], [main], [], [AC_MSG_ERROR([cannot find usrp libraries])]) 26 AC_CHECK_HEADERS([db_base.h], [], [AC_MSG_ERROR([cannot find db_base header file])]) 21 27 AC_CHECK_HEADERS([usrp_standard.h], [], [AC_MSG_ERROR([cannot find usrp_standard header file])]) 22 AC_CHECK_HEADERS([usrp_dbid.h], [], [AC_MSG_ERROR([cannot find usrp_dbid header file])])23 AC_CHECK_HEADERS([usrp_prims.h], [], [AC_MSG_ERROR([cannot find usrp_prims header file])])24 28 25 29 AC_CHECK_LIB([standardInterfaces], [main], [], [AC_MSG_ERROR([cannot find standardInterfaces])]) -
ossiedev/branches/ttsou/dist/platform/USRP/reconf
r4522 r8606 1 1 #!/bin/sh 2 2 3 rm - f config.cache4 aclocal 3 rm -rf config.cache autom4te*.cache 4 aclocal -I config 5 5 autoconf 6 6 automake --foreign --add-missing -
ossiedev/branches/ttsou/dist/platform/USRP/src/USRP.cpp
r4522 r8606 22 22 ****************************************************************************/ 23 23 24 // Defining LOG_DATA writes the I channel data sent to the USRP to I_out.dat 25 //#define LOG_DATA 26 24 #include <byteswap.h> 27 25 #include <iostream> 28 #include <string>29 #ifdef LOG_DATA30 #include <fstream>31 #endif32 33 #include <byteswap.h>34 26 35 27 #include "ossie/cf.h" … … 39 31 #include "ossie/debug.h" 40 32 41 42 33 #include "USRP.h" 43 #include "flex.h"44 #include "basic.h"45 #include "lf.h"46 #include "dbsrx.h"47 #include "tvrx.h"48 34 49 35 USRP_i::USRP_i(char *id, char *label, char *profile) : 50 36 Device_impl(id, label, profile), 51 rx_db0_control(NULL),52 rx_db1_control(NULL),53 tx_db0_control(NULL),54 tx_db1_control(NULL),55 37 set_rx_packet_count(-1), 56 38 rx_packet_count(1024), … … 60 42 complex(true), 61 43 rx_overruns(0), 62 rx_active(0), 63 tx_active(0) 64 { 65 // Create device ports 44 rx_active(false), 45 tx_active(false) 46 { 66 47 // Create USRP Control ports for TX and RX 67 68 48 rx_control_port = new USRP_RX_Control_i(this, "RX_Control", "DomainName1"); 69 70 49 tx_control_port = new USRP_TX_Control_i(this, "TX_Control", "DomainName1"); 71 50 72 51 // Create the ports for TX data 73 74 52 tx_data_port = new standardInterfaces_i::complexShort_p("TX_Data", "DomainName1"); 75 53 76 54 // Create the ports for RX Data 77 78 55 rx_data_1_port = new standardInterfaces_i::complexShort_u("RX_Data_1", "DomainName1"); 79 56 rx_data_2_port = new standardInterfaces_i::complexShort_u("RX_Data_2", "DomainName1"); 80 81 57 } 82 58 83 59 void USRP_i::start() throw (CF::Resource::StartError, CORBA::SystemException) 84 85 60 { 86 61 DEBUG(3, USRP, "Start USRP called") 87 88 62 } 89 63 90 64 void USRP_i::stop() throw (CF::Resource::StopError, CORBA::SystemException) 91 92 65 { 93 66 DEBUG(3, USRP, "Stop USRP called") 94 95 67 } 96 68 … … 117 89 } 118 90 119 void USRP_i::PrintDaughterboardWarning(const char * db_name) {120 std::cout << "The daughterboard is not yet tested: " << db_name << std::endl121 << "Please contact OSSIE team to verify and activate. " << std::endl122 << " http://ossie-dev.mprg.org:8080/trac" << std::endl;123 }124 125 91 void USRP_i::initialize() throw (CF::LifeCycle::InitializeError, CORBA::SystemException) 126 127 92 { 128 93 DEBUG(3, USRP, "USRP Initialize called") … … 135 100 } 136 101 137 //usrp_tx = usrp_standard_tx::make(0,512, 1, 0xba98, 4096, 16);138 102 usrp_tx = usrp_standard_tx::make(0,512); 139 103 … … 143 107 } 144 108 145 146 // Check for RX daughterboards 147 109 // Check for daughterboards and assign first subdevice 148 110 rx_db0 = usrp_rx->daughterboard_id(0); 149 111 rx_db1 = usrp_rx->daughterboard_id(1); 112 rx_db0_control = usrp_rx->db(0)[0]; 113 rx_db1_control = usrp_rx->db(1)[0]; 114 115 tx_db0 = usrp_tx->daughterboard_id(0); 116 tx_db1 = usrp_tx->daughterboard_id(1); 117 tx_db0_control = usrp_tx->db(0)[0]; 118 tx_db1_control = usrp_tx->db(1)[0]; 150 119 151 120 DEBUG(1, USRP, "RX daughterboard slot 0 : " << usrp_dbid_to_string(rx_db0)) 152 121 DEBUG(1, USRP, "RX daughterboard slot 1 : " << usrp_dbid_to_string(rx_db1)) 153 154 switch (rx_db0) {155 case USRP_DBID_FLEX_400_RX:156 rx_db0_control = new db_flex400_rx(usrp_rx, 0);157 break;158 case USRP_DBID_FLEX_400_RX_MIMO_A:159 //rx_db0_control = new db_flex400_rx_mimo_a(usrp_rx, 0);160 PrintDaughterboardWarning("USRP_DBID_FLEX_400_RX_MIMO_A");161 break;162 case USRP_DBID_FLEX_400_RX_MIMO_B:163 rx_db0_control = new db_flex400_rx_mimo_b(usrp_rx, 0);164 break;165 case USRP_DBID_FLEX_900_RX:166 //rx_db0_control = new db_flex900_rx(usrp_rx, 0);167 PrintDaughterboardWarning("USRP_DBID_FLEX_900_RX");168 break;169 case USRP_DBID_FLEX_900_RX_MIMO_A:170 //rx_db0_control = new db_flex900_rx_mimo_a(usrp_rx, 0);171 PrintDaughterboardWarning("USRP_DBID_FLEX_900_MIMO_A");172 break;173 case USRP_DBID_FLEX_900_RX_MIMO_B:174 rx_db0_control = new db_flex900_rx_mimo_b(usrp_rx, 0);175 break;176 case USRP_DBID_FLEX_1200_RX:177 //rx_db0_control = new db_flex1200_rx(usrp_rx, 0);178 PrintDaughterboardWarning("USRP_DBID_FLEX_1200_RX");179 break;180 case USRP_DBID_FLEX_1200_RX_MIMO_A:181 //rx_db0_control = new db_flex1200_rx_mimo_a(usrp_rx, 0);182 PrintDaughterboardWarning("USRP_DBID_FLEX_1200_RX_MIMO_A");183 break;184 case USRP_DBID_FLEX_1200_RX_MIMO_B:185 rx_db0_control = new db_flex1200_rx_mimo_b(usrp_rx, 0);186 break;187 /*188 case USRP_DBID_FLEX_1800_RX:189 //rx_db0_control = new db_flex1800_rx(usrp_rx, 0);190 PrintDaughterboardWarning("USRP_DBID_FLEX_1800_RX");191 break;192 case USRP_DBID_FLEX_1800_RX_MIMO_A:193 //rx_db0_control = new db_flex1800_rx_mimo_a(usrp_rx, 0);194 PrintDaughterboardWarning("USRP_DBID_FLEX_1800_RX_MIMO_A");195 break;196 case USRP_DBID_FLEX_1800_RX_MIMO_B:197 //rx_db0_control = new db_flex1800_rx_mimo_b(usrp_rx, 0);198 PrintDaughterboardWarning("USRP_DBID_FLEX_1800_RX_MIMO_B");199 break;200 */201 case USRP_DBID_FLEX_2400_RX:202 rx_db0_control = new db_flex2400_rx(usrp_rx, 0);203 break;204 case USRP_DBID_FLEX_2400_RX_MIMO_A:205 //rx_db0_control = new db_flex2400_rx_mimo_a(usrp_rx, 0);206 PrintDaughterboardWarning("USRP_DBID_FLEX_2400_RX_MIMO_A");207 break;208 case USRP_DBID_FLEX_2400_RX_MIMO_B:209 //rx_db0_control = new db_flex2400_rx_mimo_b(usrp_rx, 0);210 PrintDaughterboardWarning("USRP_DBID_FLEX_2400_RX_MIMO_B");211 break;212 case USRP_DBID_BASIC_RX:213 rx_db0_control = new db_basic_rx(usrp_rx, 0);214 break;215 case USRP_DBID_DBS_RX:216 rx_db0_control = new dbsrx(usrp_rx, 0);217 break;218 case USRP_DBID_DBS_RX_REV_2_1:219 //rx_db0_control = new dbsrx(usrp_rx, 0);220 PrintDaughterboardWarning("USRP_DBID_DBS_RX_REV_2_1");221 break;222 case USRP_DBID_TV_RX:223 //rx_db0_control = new tvrx(usrp_rx, 0);224 PrintDaughterboardWarning("USRP_DBID_TV_RX");225 break;226 case USRP_DBID_TV_RX_REV_2:227 //rx_db0_control = new tvrx_rev2(usrp_rx, 0);228 PrintDaughterboardWarning("USRP_DBID_TV_RX_REV_2");229 break;230 /*231 case USRP_DBID_TV_RX_REV_3:232 //rx_db0_control = new tvrx_rev3(usrp_rx, 0);233 PrintDaughterboardWarning("USRP_DBID_TV_RX_REV_3");234 break;235 */236 case USRP_DBID_LF_RX:237 rx_db0_control = new db_lf_rx(usrp_rx, 0);238 break;239 }240 241 switch (rx_db1) {242 case USRP_DBID_FLEX_400_RX:243 rx_db1_control = new db_flex400_rx(usrp_rx, 1);244 break;245 case USRP_DBID_FLEX_400_RX_MIMO_A:246 //rx_db1_control = new db_flex400_rx_mimo_a(usrp_rx, 1);247 PrintDaughterboardWarning("USRP_DBID_FLEX_400_MIMO_A");248 break;249 case USRP_DBID_FLEX_400_RX_MIMO_B:250 rx_db1_control = new db_flex400_rx_mimo_b(usrp_rx, 1);251 break;252 case USRP_DBID_FLEX_900_RX:253 //rx_db1_control = new db_flex900_rx(usrp_rx, 1);254 PrintDaughterboardWarning("USRP_DBID_FLEX_900_RX");255 break;256 case USRP_DBID_FLEX_900_RX_MIMO_A:257 //rx_db1_control = new db_flex900_rx_mimo_a(usrp_rx, 1);258 PrintDaughterboardWarning("USRP_DBID_FLEX_900_RX_MIMO_A");259 break;260 case USRP_DBID_FLEX_900_RX_MIMO_B:261 rx_db1_control = new db_flex900_rx_mimo_b(usrp_rx, 1);262 break;263 case USRP_DBID_FLEX_1200_RX:264 //rx_db1_control = new db_flex1200_rx(usrp_rx, 1);265 PrintDaughterboardWarning("USRP_DBID_FLEX_1200_RX");266 break;267 case USRP_DBID_FLEX_1200_RX_MIMO_A:268 //rx_db1_control = new db_flex1200_rx_mimo_a(usrp_rx, 1);269 PrintDaughterboardWarning("USRP_DBID_FLEX_1200_RX_MIMO_A");270 break;271 case USRP_DBID_FLEX_1200_RX_MIMO_B:272 rx_db1_control = new db_flex1200_rx_mimo_b(usrp_rx, 1);273 break;274 /*275 case USRP_DBID_FLEX_1800_RX:276 //rx_db1_control = new db_flex1800_rx(usrp_rx, 1);277 PrintDaughterboardWarning("USRP_DBID_FLEX_1800_RX");278 break;279 case USRP_DBID_FLEX_1800_RX_MIMO_A:280 //rx_db1_control = new db_flex1800_rx_mimo_a(usrp_rx, 1);281 PrintDaughterboardWarning("USRP_DBID_FLEX_1800_RX_MIMO_A");282 break;283 case USRP_DBID_FLEX_1800_RX_MIMO_B:284 //rx_db1_control = new db_flex1800_rx_mimo_b(usrp_rx, 1);285 PrintDaughterboardWarning("USRP_DBID_FLEX_1800_RX_MIMO_B");286 break;287 */288 case USRP_DBID_FLEX_2400_RX:289 rx_db1_control = new db_flex2400_rx(usrp_rx, 1);290 break;291 case USRP_DBID_FLEX_2400_RX_MIMO_A:292 //rx_db1_control = new db_flex2400_rx_mimo_a(usrp_rx, 1);293 PrintDaughterboardWarning("USRP_DBID_FLEX_2400_RX_MIMO_A");294 break;295 case USRP_DBID_FLEX_2400_RX_MIMO_B:296 //rx_db1_control = new db_flex2400_rx_mimo_b(usrp_rx, 1);297 PrintDaughterboardWarning("USRP_DBID_FLEX_2400_RX_MIMO_B");298 break;299 case USRP_DBID_BASIC_RX:300 rx_db1_control = new db_basic_rx(usrp_rx, 1);301 break;302 case USRP_DBID_DBS_RX:303 rx_db1_control = new dbsrx(usrp_rx, 1);304 break;305 case USRP_DBID_DBS_RX_REV_2_1:306 //rx_db1_control = new dbsrx(usrp_rx, 1);307 PrintDaughterboardWarning("USRP_DBID_DBS_RX_REV_2_1");308 break;309 case USRP_DBID_TV_RX:310 //rx_db1_control = new tvrx(usrp_rx, 1);311 PrintDaughterboardWarning("USRP_DBID_TV_RX");312 break;313 case USRP_DBID_TV_RX_REV_2:314 //rx_db1_control = new tvrx_rev2(usrp_rx, 1);315 PrintDaughterboardWarning("USRP_DBID_TV_RX_REV_2");316 break;317 /*318 case USRP_DBID_TV_RX_REV_3:319 //rx_db1_control = new tvrx_rev3(usrp_rx, 1);320 std::cout << "The daughterboard is not yet tested: Please contact OSSIE team to verify and activate. http://ossie-dev.mprg.org:8080/trac" << std::endl;321 break;322 */323 case USRP_DBID_LF_RX:324 rx_db1_control = new db_lf_rx(usrp_rx, 1);325 break;326 327 }328 329 // Check for TX daughterboards330 331 tx_db0 = usrp_tx->daughterboard_id(0);332 tx_db1 = usrp_tx->daughterboard_id(1);333 334 switch (tx_db0) {335 case USRP_DBID_FLEX_400_TX:336 tx_db0_control = new db_flex400_tx(usrp_tx, 0);337 break;338 case USRP_DBID_FLEX_400_TX_MIMO_A:339 //tx_db0_control = new db_flex400_tx_mimo_a(usrp_tx, 0);340 PrintDaughterboardWarning("USRP_DBID_FLEX_400_TX_MIMO_A");341 break;342 case USRP_DBID_FLEX_400_TX_MIMO_B:343 tx_db0_control = new db_flex400_tx_mimo_b(usrp_tx, 0);344 break;345 case USRP_DBID_FLEX_900_TX:346 //tx_db0_control = new db_flex900_tx(usrp_tx, 0);347 PrintDaughterboardWarning("USRP_DBID_FLEX_900_TX");348 break;349 case USRP_DBID_FLEX_900_TX_MIMO_A:350 //tx_db0_control = new db_flex900_tx_mimo_a(usrp_tx, 0);351 PrintDaughterboardWarning("USRP_DBID_FLEX_900_TX_MIMO_A");352 break;353 case USRP_DBID_FLEX_900_TX_MIMO_B:354 tx_db0_control = new db_flex900_tx_mimo_b(usrp_tx, 0);355 break;356 case USRP_DBID_FLEX_1200_TX:357 //tx_db0_control = new db_flex1200_tx(usrp_tx, 0);358 PrintDaughterboardWarning("USRP_DBID_FLEX_1200_TX");359 break;360 case USRP_DBID_FLEX_1200_TX_MIMO_A:361 //tx_db0_control = new db_flex1200_tx_mimo_a(usrp_tx, 0);362 PrintDaughterboardWarning("USRP_DBID_FLEX_1200_TX_MIMO_A");363 break;364 case USRP_DBID_FLEX_1200_TX_MIMO_B:365 tx_db0_control = new db_flex1200_tx_mimo_b(usrp_tx, 0);366 break;367 /*368 case USRP_DBID_FLEX_1800_TX:369 //tx_db0_control = new db_flex1800_tx(usrp_tx, 0);370 PrintDaughterboardWarning("USRP_DBID_FLEX_1800");371 break;372 case USRP_DBID_FLEX_1800_TX_MIMO_A:373 //tx_db0_control = new db_flex1800_tx_mimo_a(usrp_tx, 0);374 PrintDaughterboardWarning("USRP_DBID_FLEX_1800_TX_MIMO_A");375 break;376 case USRP_DBID_FLEX_1800_TX_MIMO_B:377 //tx_db0_control = new db_flex1800_tx_mimo_b(usrp_tx, 0);378 PrintDaughterboardWarning("USRP_DBID_FLEX_1800_TX_MIMO_B");379 break;380 */381 case USRP_DBID_FLEX_2400_TX:382 tx_db0_control = new db_flex2400_tx(usrp_tx, 0);383 break;384 case USRP_DBID_FLEX_2400_TX_MIMO_A:385 //tx_db0_control = new db_flex2400_tx_mimo_a(usrp_tx, 0);386 PrintDaughterboardWarning("USRP_DBID_FLEX_2400_TX_MIMO_A");387 break;388 case USRP_DBID_FLEX_2400_TX_MIMO_B:389 //tx_db0_control = new db_flex2400_tx_mimo_b(usrp_tx, 0);390 PrintDaughterboardWarning("USRP_DBID_FLEX_2400_TX_MIMO_B");391 break;392 case USRP_DBID_BASIC_TX:393 tx_db0_control = new db_basic_tx(usrp_tx, 0);394 break;395 case USRP_DBID_LF_TX:396 tx_db0_control = new db_lf_tx(usrp_tx, 0);397 break;398 399 400 }401 402 switch (tx_db1) {403 case USRP_DBID_FLEX_400_TX:404 tx_db1_control = new db_flex400_tx(usrp_tx, 1);405 break;406 case USRP_DBID_FLEX_400_TX_MIMO_A:407 //tx_db1_control = new db_flex400_tx_mimo_a(usrp_tx, 1);408 PrintDaughterboardWarning("USRP_DBID_FLEX_400_TX_MIMO_A");409 break;410 case USRP_DBID_FLEX_400_TX_MIMO_B:411 tx_db1_control = new db_flex400_tx_mimo_b(usrp_tx, 1);412 break;413 case USRP_DBID_FLEX_900_TX:414 //tx_db1_control = new db_flex900_tx(usrp_tx, 1);415 PrintDaughterboardWarning("USRP_DBID_FLEX_900_TX");416 break;417 case USRP_DBID_FLEX_900_TX_MIMO_A:418 //tx_db1_control = new db_flex900_tx_mimo_a(usrp_tx, 1);419 PrintDaughterboardWarning("USRP_DBID_FLEX_900_TX_MIMO_A");420 break;421 case USRP_DBID_FLEX_900_TX_MIMO_B:422 tx_db1_control = new db_flex900_tx_mimo_b(usrp_tx, 1);423 break;424 case USRP_DBID_FLEX_1200_TX:425 //tx_db1_control = new db_flex1200_tx(usrp_tx, 1);426 PrintDaughterboardWarning("USRP_DBID_FLEX_1200_TX");427 break;428 case USRP_DBID_FLEX_1200_TX_MIMO_A:429 //tx_db1_control = new db_flex1200_tx_mimo_a(usrp_tx, 1);430 PrintDaughterboardWarning("USRP_DBID_FLEX_1200_TX_MIMO_A");431 break;432 case USRP_DBID_FLEX_1200_TX_MIMO_B:433 tx_db1_control = new db_flex1200_tx_mimo_b(usrp_tx, 1);434 break;435 /*436 case USRP_DBID_FLEX_1800_TX:437 //tx_db1_control = new db_flex1800_tx(usrp_tx, 1);438 PrintDaughterboardWarning("USRP_DBID_FLEX_1800");439 break;440 case USRP_DBID_FLEX_1800_TX_MIMO_A:441 //tx_db1_control = new db_flex1800_tx_mimo_a(usrp_tx, 1);442 PrintDaughterboardWarning("USRP_DBID_FLEX_1800_TX_MIMO_A");443 break;444 case USRP_DBID_FLEX_1800_TX_MIMO_B:445 //tx_db1_control = new db_flex1800_tx_mimo_b(usrp_tx, 1);446 PrintDaughterboardWarning("USRP_DBID_FLEX_1800_TX_MIMO_B");447 break;448 */449 case USRP_DBID_FLEX_2400_TX:450 tx_db1_control = new db_flex2400_tx(usrp_tx, 1);451 break;452 case USRP_DBID_FLEX_2400_TX_MIMO_A:453 //tx_db1_control = new db_flex2400_tx_mimo_a(usrp_tx, 1);454 PrintDaughterboardWarning("USRP_DBID_FLEX_2400_TX_MIMO_A");455 break;456 case USRP_DBID_FLEX_2400_TX_MIMO_B:457 //tx_db1_control = new db_flex2400_tx_mimo_b(usrp_tx, 1);458 PrintDaughterboardWarning("USRP_DBID_FLEX_2400_TX_MIMO_B");459 break;460 case USRP_DBID_BASIC_TX:461 tx_db1_control = new db_basic_tx(usrp_tx, 1);462 break;463 case USRP_DBID_LF_TX:464 tx_db1_control = new db_lf_tx(usrp_tx, 1);465 break;466 467 }468 469 470 122 DEBUG(1, USRP, "TX daughterboard slot 0 : " << usrp_dbid_to_string(tx_db0)) 471 123 DEBUG(1, USRP, "TX daughterboard slot 1 : " << usrp_dbid_to_string(tx_db1)) … … 473 125 } 474 126 475 476 127 void USRP_i::configure(const CF::Properties &configProperties) 477 throw (CORBA::SystemException, 478 CF::PropertySet::InvalidConfiguration, 128 throw (CORBA::SystemException, CF::PropertySet::InvalidConfiguration, 479 129 CF::PropertySet::PartialConfiguration) 480 130 { … … 482 132 } 483 133 484 void USRP_i::query(CF::Properties &configProperties) throw (CORBA::SystemException, CF::UnknownProperties) 485 { 486 487 } 488 489 490 void USRP_i::releaseObject() throw (CF::LifeCycle::ReleaseError, CORBA::SystemException) 491 134 void USRP_i::query(CF::Properties &configProperties) 135 throw (CORBA::SystemException, CF::UnknownProperties) 136 { 137 138 } 139 140 141 void USRP_i::releaseObject() 142 throw (CF::LifeCycle::ReleaseError, CORBA::SystemException) 492 143 { 493 144 … … 496 147 497 148 void USRP_i::rx_data_process() 498 499 149 { 500 150 short *rx_buffer; … … 534 184 if (rx_packet_count != -1) 535 185 --rx_packet_count; 536 537 186 } 538 187 … … 547 196 // Helper function for tx_data_process 548 197 inline static void tx_with_usrp( 549 usrp_standard_tx *usrp_tx,198 usrp_standard_tx_sptr usrp_tx, 550 199 short *tx_buf, 551 200 unsigned int tx_buf_len, … … 588 237 short tx_buf[tx_buf_len]; 589 238 590 #ifdef LOG_DATA591 std::ofstream *ofile = new std::ofstream("I_out.dat");592 #endif593 594 239 DEBUG(3, USRP, "Starting tx_data_process thread.") 595 240 … … 599 244 600 245 tx_data_port->getData(I_in, Q_in); 601 602 246 unsigned int data_length(I_in->length()); 603 247 … … 605 249 tx_buf[tx_buf_idx] = convertToLE((*I_in)[i]); 606 250 ++tx_buf_idx; 607 #ifdef LOG_DATA608 *ofile << (*I_in)[i] << std::endl;609 #endif610 251 tx_buf[tx_buf_idx] = convertToLE((*Q_in)[i]); 611 252 ++tx_buf_idx; … … 616 257 } 617 258 } 618 619 259 tx_data_port->bufferEmptied(); 620 260 } 621 #ifdef LOG_DATA622 delete ofile;623 #endif624 261 625 262 DEBUG(3, USRP, "Exiting tx_data_process thread.") 626 263 usrp_tx->stop(); 627 264 tx_thread->exit(); 628 } 265 266 } -
ossiedev/branches/ttsou/dist/platform/USRP/src/USRP.h
r5860 r8606 39 39 #include "ossie/Device_impl.h" 40 40 41 #include "flex.h"42 #include "dbsrx.h"43 #include "tvrx.h"44 45 41 // Definitions for provides ports 46 42 class USRP_i; 47 43 48 class USRP_RX_Control_i : public standardInterfaces_i::RX_Control_p 49 50 { 51 44 class USRP_RX_Control_i : public standardInterfaces_i::RX_Control_p, 45 boost::noncopyable 46 { 52 47 public: 53 48 USRP_RX_Control_i(USRP_i *_usrp, const char* _name, const char* _domain); 49 54 50 void set_number_of_channels(CORBA::ULong num); 55 51 void get_number_of_channels(CORBA::ULong &num); 56 57 void get_gain_range(CORBA::ULong channel, CORBA::Float &gmin,CORBA::Float &gmax, CORBA::Float &gstep);52 void get_gain_range(CORBA::ULong channel, CORBA::Float &gmin, 53 CORBA::Float &gmax, CORBA::Float &gstep); 58 54 void set_gain(CORBA::ULong channel, CORBA::Float gain); 59 55 void get_gain(CORBA::ULong channel, CORBA::Float &gain); 60 61 void get_frequency_range(CORBA::ULong channel, CORBA::Float &fmin,CORBA::Float &fmax, CORBA::Float &fstep);56 void get_frequency_range(CORBA::ULong channel, CORBA::Float &fmin, 57 CORBA::Float &fmax, CORBA::Float &fstep); 62 58 void set_frequency(CORBA::ULong channel, CORBA::Float f); 63 59 void get_frequency(CORBA::ULong channel, CORBA::Float &f); … … 67 63 68 64 void set_values(const CF::Properties &values); 69 70 65 void set_decimation_rate(CORBA::ULong channel, CORBA::ULong M); 71 void get_decimation_range(CORBA::ULong channel, CORBA::ULong &dmin, CORBA::ULong &dmax, CORBA::ULong &dstep);72 66 void get_decimation_range(CORBA::ULong channel, CORBA::ULong &dmin, 67 CORBA::ULong &dmax, CORBA::ULong &dstep); 73 68 void set_data_packet_size(CORBA::ULong channel, CORBA::ULong N); 74 69 75 70 private: 76 71 USRP_RX_Control_i(); // No default constructor 77 USRP_RX_Control_i(const USRP_RX_Control_i &); // No copying78 79 72 USRP_i *usrp; 80 81 float db_lo_freq; 82 float db_lo_offset; 83 bool lo_locked; 84 85 }; 86 87 class USRP_TX_Control_i : public standardInterfaces_i::TX_Control_p 88 73 }; 74 75 class USRP_TX_Control_i : public standardInterfaces_i::TX_Control_p, 76 boost::noncopyable 89 77 { 90 78 public: 91 79 USRP_TX_Control_i(USRP_i *_usrp, const char* _name, const char* _domain); 80 92 81 void set_number_of_channels(CORBA::ULong num); 93 82 void get_number_of_channels(CORBA::ULong &num); 94 95 void get_gain_range(CORBA::ULong channel, CORBA::Float &gmin,CORBA::Float &gmax, CORBA::Float &gstep);83 void get_gain_range(CORBA::ULong channel, CORBA::Float &gmin, 84 CORBA::Float &gmax, CORBA::Float &gstep); 96 85 void set_gain(CORBA::ULong channel, CORBA::Float gain); 97 86 void get_gain(CORBA::ULong channel, CORBA::Float &gain); 98 99 void get_frequency_range(CORBA::ULong channel, CORBA::Float &fmin,CORBA::Float &fmax, CORBA::Float &fstep);87 void get_frequency_range(CORBA::ULong channel, CORBA::Float &fmin, 88 CORBA::Float &fmax, CORBA::Float &fstep); 100 89 void set_frequency(CORBA::ULong channel, CORBA::Float f); 101 90 void get_frequency(CORBA::ULong channel, CORBA::Float &f); … … 105 94 106 95 void set_values(const CF::Properties &values); 107 108 96 void set_interpolation_rate(CORBA::ULong channel, CORBA::ULong I); 109 void get_interpolation_range(CORBA::ULong channel, CORBA::ULong &imin, CORBA::ULong &imax, CORBA::ULong &istep); 97 void get_interpolation_range(CORBA::ULong channel, CORBA::ULong &imin, 98 CORBA::ULong &imax, CORBA::ULong &istep); 110 99 111 100 private: 112 101 USRP_TX_Control_i(); // No default constructor 113 USRP_TX_Control_i(const USRP_TX_Control_i &); // No copying114 115 102 USRP_i *usrp; 116 117 float db_lo_freq;118 float db_lo_offset;119 bool lo_locked;120 103 }; 121 104 122 105 class TX_data_i : public POA_standardInterfaces::complexShort 123 124 106 { 125 107 public: … … 127 109 ~TX_data_i(); 128 110 129 void pushPacket(const PortTypes::ShortSequence &I, const PortTypes::ShortSequence &Q); 111 void pushPacket(const PortTypes::ShortSequence &I, 112 const PortTypes::ShortSequence &Q); 130 113 131 114 private: … … 135 118 unsigned int tx_buf_idx; 136 119 int tx_buf_len; 137 138 120 unsigned int tx_underruns; 139 121 }; 140 122 141 // Definitions for uses ports 142 143 // Main USRP device definition 144 void rx_data_process(void *data); 145 146 class USRP_i : public virtual Device_impl 147 123 class USRP_i : public virtual Device_impl, boost::noncopyable 148 124 { 149 125 friend class USRP_RX_Control_i; 150 126 friend class USRP_TX_Control_i; 151 127 152 friend void rx_data_process(void *);153 154 128 public: 155 129 USRP_i(char *id, char *label, char *profile); 156 130 157 static void do_rx_data_process(void *u) {((USRP_i *)u)->rx_data_process(); 158 static void do_tx_data_process(void *u) {((USRP_i *)u)->tx_data_process(); 131 static void do_rx_data_process(void *u) {((USRP_i *)u)->rx_data_process();}; 132 static void do_tx_data_process(void *u) {((USRP_i *)u)->tx_data_process();}; 159 133 160 134 // Methods from the SCA definition 161 void start() throw (CF::Resource::StartError, CORBA::SystemException); 162 void stop() throw (CF::Resource::StopError, CORBA::SystemException); 163 CORBA::Object_ptr getPort(const char* portName) throw(CF::PortSupplier::UnknownPort, CORBA::SystemException); 164 void initialize() throw (CF::LifeCycle::InitializeError, CORBA::SystemException); 165 void configure(const CF::Properties &configProperties) throw (CORBA::SystemException, CF::PropertySet::InvalidConfiguration, CF::PropertySet::PartialConfiguration); 166 void query(CF::Properties &configProperties) throw (CORBA::SystemException, CF::UnknownProperties); 167 168 void releaseObject() throw (CF::LifeCycle::ReleaseError, CORBA::SystemException); 135 void start() 136 throw (CF::Resource::StartError, CORBA::SystemException); 137 void stop() 138 throw (CF::Resource::StopError, CORBA::SystemException); 139 CORBA::Object_ptr getPort(const char* portName) 140 throw(CF::PortSupplier::UnknownPort, CORBA::SystemException); 141 void initialize() 142 throw (CF::LifeCycle::InitializeError, CORBA::SystemException); 143 void configure(const CF::Properties &configProperties) 144 throw (CORBA::SystemException, CF::PropertySet::InvalidConfiguration, 145 CF::PropertySet::PartialConfiguration); 146 void query(CF::Properties &configProperties) 147 throw (CORBA::SystemException, CF::UnknownProperties); 148 void releaseObject() 149 throw (CF::LifeCycle::ReleaseError, CORBA::SystemException); 169 150 170 151 omni_mutex rx_run; … … 174 155 omni_mutex tx_control_access; 175 156 176 177 157 private: 178 158 USRP_i(); // No default constructor 179 USRP_i(const USRP_i&); // No copying180 181 // RX data processing thread182 // static void rx_data_process(void * data); ///\todo verify statis is the online way183 184 /// Prints warning about unsupported USRP daughter boards185 void PrintDaughterboardWarning(const char * db_name);186 159 187 160 // Port objects … … 195 168 196 169 // usrp variables 197 198 usrp_standard_rx *usrp_rx; 199 usrp_standard_tx *usrp_tx; 170 usrp_standard_rx_sptr usrp_rx; 171 usrp_standard_tx_sptr usrp_tx; 200 172 201 173 // Daughterboard data 174 // 175 // A vector of subdevices is associated for each daughterboard with libusrp. 176 // Only a single subdevice (the first) is supported at this time. 202 177 int rx_db0; 203 178 int rx_db1; … … 205 180 int tx_db1; 206 181 207 db_base *rx_db0_control;208 db_base *rx_db1_control;209 db_base *tx_db0_control;210 db_base *tx_db1_control;182 db_base_sptr rx_db0_control; 183 db_base_sptr rx_db1_control; 184 db_base_sptr tx_db0_control; 185 db_base_sptr tx_db1_control; 211 186 212 187 omni_thread *rx_thread; … … 226 201 bool rx_active; 227 202 bool tx_active; 228 229 }; 203 }; -
ossiedev/branches/ttsou/dist/platform/USRP/src/main.cpp
r8105 r8606 23 23 24 24 #include <iostream> 25 #include <cstdlib>26 25 #include <sched.h> 27 26 … … 31 30 #include "USRP.h" 32 31 33 34 32 int main(int argc, char* argv[]) 35 36 33 { 37 38 34 if (argc != 4) { 39 std::cerr << argv[0] << " <identifier> <usage name> <software profile>" << std::endl; 35 std::cerr << argv[0] << " <identifier>" 36 << " <usage name>" 37 << " <software profile>" << std::endl; 40 38 exit (-1); 41 39 } 42 43 ossieDebugLevel = 3;44 45 struct sched_param prio;46 47 prio.sched_priority = 5;48 49 int rc = sched_setscheduler(0, SCHED_RR, &prio);50 51 if (rc < 0)52 std::cerr << "Failed to set RR scheduler for USRP device." << std::endl;53 54 ossieSupport::ORB *orb = new ossieSupport::ORB;55 40 56 41 char *id = argv[1]; … … 58 43 char *profile = argv[3]; 59 44 45 ossieDebugLevel = 3; 60 46 47 ossieSupport::ORB *orb = new ossieSupport::ORB; 61 48 USRP_i* usrp_servant; 62 49 CF::Device_var usrp_var; 63 50 64 51 // Create the USRP device servant and object reference 65 66 52 usrp_servant = new USRP_i(id, label, profile); 67 53 usrp_var = usrp_servant->_this(); … … 71 57 orb->bind_object_to_name((CORBA::Object_ptr) usrp_var, objName.c_str()); 72 58 73 74 59 // Start the orb 75 60 orb->orb->run(); 76 77 61 } -
ossiedev/branches/ttsou/dist/platform/USRP/src/port_impl.cpp
r8274 r8606 23 23 24 24 #include <iostream> 25 26 25 #include <omniORB4/CORBA.h> 27 28 26 #include "ossie/debug.h" 29 30 27 #include "USRP.h" 31 #include "flex.h" 32 33 USRP_TX_Control_i::USRP_TX_Control_i(USRP_i *_usrp, const char* _name, const char* _domain) : standardInterfaces_i::TX_Control_p(_name, _domain), usrp(_usrp), db_lo_freq(0), db_lo_offset(-8e6), lo_locked(false) 28 29 USRP_TX_Control_i::USRP_TX_Control_i(USRP_i *_usrp, const char* _name, const char* _domain) : standardInterfaces_i::TX_Control_p(_name, _domain), usrp(_usrp) 34 30 { 35 31 DEBUG(3, USRP, "TX Control port constructor called") … … 45 41 void USRP_TX_Control_i::get_number_of_channels(CORBA::ULong &num) 46 42 { 47 omni_mutex_lock l(usrp->tx_control_access);48 43 num = usrp->usrp_tx->nchannels(); 49 44 } … … 51 46 void USRP_TX_Control_i::get_gain_range(CORBA::ULong channel, CORBA::Float &gmin, CORBA::Float &gmax, CORBA::Float &gstep) 52 47 { 53 omni_mutex_lock l(usrp->tx_control_access); 54 if (channel == 0) { 55 if (usrp->tx_db0_control) 56 usrp->tx_db0_control->get_gain_range(gmin, gmax, gstep); 57 } else if (channel == 1) { 58 if (usrp->tx_db1_control) 59 usrp->tx_db1_control->get_gain_range(gmin, gmax, gstep); 48 if (channel == 0) { 49 if (usrp->tx_db0_control) { 50 gmin = usrp->tx_db0_control->gain_min(); 51 gmax = usrp->tx_db0_control->gain_max(); 52 gstep = usrp->tx_db0_control->gain_db_per_step(); 53 } 54 } else if (channel == 1) { 55 if (usrp->tx_db1_control) { 56 gmin = usrp->tx_db1_control->gain_min(); 57 gmax = usrp->tx_db1_control->gain_max(); 58 gstep = usrp->tx_db1_control->gain_db_per_step(); 59 } 60 60 } else { 61 61 return; ///\todo throw bad channel exception … … 67 67 omni_mutex_lock l(usrp->tx_control_access); 68 68 if (channel == 0) { 69 if (usrp->tx_db0_control) 69 if (usrp->tx_db0_control) { 70 70 usrp->tx_db0_control->set_gain(gain); 71 } 71 72 } else if (channel == 1) { 72 73 if (usrp->tx_db1_control) … … 79 80 void USRP_TX_Control_i::get_gain(CORBA::ULong channel, CORBA::Float &gain) 80 81 { 81 82 gain = usrp->usrp_tx->pga(channel); 82 83 } 83 84 84 85 void USRP_TX_Control_i::get_frequency_range(CORBA::ULong channel, CORBA::Float &fmin, CORBA::Float &fmax, CORBA::Float &fstep) 85 86 { 86 omni_mutex_lock l(usrp->tx_control_access); 87 if (channel == 0) { 88 if (usrp->tx_db0_control) 89 usrp->tx_db0_control->get_freq_range(fmin, fmax, fstep); 90 } else if (channel == 1) { 91 if (usrp->tx_db1_control) 92 usrp->tx_db1_control->get_freq_range(fmin, fmax, fstep); 87 if (channel == 0) { 88 if (usrp->tx_db0_control) { 89 fmin = usrp->tx_db0_control->freq_min(); 90 fmax = usrp->tx_db0_control->freq_max(); 91 fstep = 0; 92 } 93 } else if (channel == 1) { 94 if (usrp->tx_db1_control) { 95 fmin = usrp->tx_db1_control->freq_min(); 96 fmax = usrp->tx_db1_control->freq_max(); 97 fstep = 0; 98 } 93 99 } else { 94 100 return; ///\todo throw bad channel exception … … 98 104 void USRP_TX_Control_i::set_frequency(CORBA::ULong channel, CORBA::Float f) 99 105 { 100 /// \todo move this into db code to avoid the test for db have lo (maybe) 101 102 class db_base *db(NULL); 103 104 omni_mutex_lock l(usrp->tx_control_access); 105 if (channel == 0) { 106 if (usrp->tx_db0_control) 107 db = usrp->tx_db0_control; 108 } else if (channel == 1) { 109 if (usrp->tx_db1_control) 110 db = usrp->tx_db1_control; 111 } else { 112 return; ///\todo throw bad channel exception 113 } 114 115 if (!db) 116 return; // No daughter board present 117 118 if (db->db_has_lo()) { 119 float fmin, fmax, fstep; 120 db->get_freq_range(fmin, fmax, fstep); 121 if ((f < fmin) || (f > fmax)) 122 return; /// \todo throw exception 123 124 if (!lo_locked) { 125 float db_lo_freq_set = f + db_lo_offset; 126 if (db_lo_freq_set < fmin) 127 db_lo_freq_set = fmin; 128 else if (db_lo_freq_set > fmax) 129 db_lo_freq_set = fmax; 130 131 db->set_db_freq(db_lo_freq_set, db_lo_freq); 132 } 133 } else 134 db_lo_freq = 0.0; 135 136 float ddc_freq = f - db_lo_freq; 137 if ((ddc_freq < 0.0) || (ddc_freq > 32e6)) 138 return; ///\todo throw an exception 139 140 usrp->usrp_tx->set_tx_freq(channel, ddc_freq); 106 DEBUG(3, USRP, "In TX Control set frequency channel: " << channel << ", frequency: " << f); 107 108 db_base_sptr db; 109 usrp_tune_result result; 110 111 omni_mutex_lock l(usrp->tx_control_access); 112 113 if (channel == 0) { 114 db = usrp->tx_db0_control; 115 } else if (channel == 1) { 116 db = usrp->tx_db1_control; 117 } else { 118 DEBUG(3, USRP, "USRP TX set_frequency (invalid channel)"); 119 return; 120 } 121 122 if (!usrp->usrp_tx->tune(channel, db, f, &result)) { 123 DEBUG(3, USRP, "USRP TX set_frequency tune failed"); 124 return; // throw exception 125 } 126 127 DEBUG(3, USRP, "USRP TX tune_result:" << 128 " baseband_freq=" << result.baseband_freq << 129 " dxc_freq=" << result.dxc_freq << 130 " residual_freq=" << result.residual_freq << 131 " inverted=" << result.inverted); 141 132 142 133 } … … 149 140 void USRP_TX_Control_i::start(CORBA::ULong channel) 150 141 { 151 152 142 omni_mutex_lock l(usrp->tx_control_access); 153 143 if (channel == 0) { … … 166 156 usrp->tx_thread = new omni_thread(USRP_i::do_tx_data_process, ((void *)usrp)); 167 157 usrp->tx_thread->start(); 168 169 158 } 170 159 171 160 void USRP_TX_Control_i::stop(CORBA::ULong channel) 172 161 { 173 174 162 omni_mutex_lock l(usrp->tx_control_access); 175 163 if (channel == 0) { … … 181 169 } 182 170 171 usrp->tx_active = false; 172 183 173 if (usrp->tx_active) 184 174 usrp->usrp_tx->stop(); 185 usrp->tx_active = false;186 175 } 187 176 … … 217 206 void USRP_TX_Control_i::set_interpolation_rate(CORBA::ULong channel, CORBA::ULong I) 218 207 { 219 220 208 // USRP interpolation rate applies to all channels, ignore channel 221 209 omni_mutex_lock l(usrp->tx_control_access); … … 225 213 void USRP_TX_Control_i::get_interpolation_range(CORBA::ULong channel, CORBA::ULong &imin, CORBA::ULong &imax, CORBA::ULong &istep) 226 214 { 227 228 215 imin = 4; 229 216 imax = 512; … … 231 218 } 232 219 233 USRP_RX_Control_i::USRP_RX_Control_i(USRP_i *_usrp, const char* _name, const char* _domain) : standardInterfaces_i::RX_Control_p(_name, _domain), usrp(_usrp) , db_lo_freq(0), db_lo_offset(-8e6), lo_locked(false)220 USRP_RX_Control_i::USRP_RX_Control_i(USRP_i *_usrp, const char* _name, const char* _domain) : standardInterfaces_i::RX_Control_p(_name, _domain), usrp(_usrp) 234 221 { 235 222 DEBUG(3, USRP, "RX Control port constructor called") … … 253 240 omni_mutex_lock l(usrp->rx_control_access); 254 241 if (channel == 0) { 255 if (usrp->rx_db0_control) 256 usrp->rx_db0_control->get_gain_range(gmin, gmax, gstep); 257 } else if (channel == 1) { 258 if (usrp->rx_db1_control) 259 usrp->rx_db1_control->get_gain_range(gmin, gmax, gstep); 242 if (usrp->rx_db0_control) { 243 gmin = usrp->rx_db0_control->gain_min(); 244 gmax = usrp->rx_db0_control->gain_max();; 245 gstep = usrp->rx_db0_control->gain_db_per_step(); 246 } 247 } else if (channel == 1) { 248 if (usrp->rx_db1_control) { 249 gmin = usrp->rx_db1_control->gain_min(); 250 gmax = usrp->rx_db1_control->gain_max();; 251 gstep = usrp->rx_db1_control->gain_db_per_step(); 252 } 260 253 } else { 261 254 return; ///\todo throw bad channel exception … … 265 258 void USRP_RX_Control_i::set_gain(CORBA::ULong channel, CORBA::Float gain) 266 259 { 260 DEBUG(1, USRP, "set gain "); 261 267 262 omni_mutex_lock l(usrp->rx_control_access); 268 263 if (channel == 0) { … … 286 281 // for now adding temp_gain and temp_aux.....PHELPS with fix it 287 282 gain = temp_gain + temp_aux; 288 289 283 } 290 284 … … 293 287 omni_mutex_lock l(usrp->rx_control_access); 294 288 if (channel == 0) { 295 if (usrp->rx_db0_control) 296 usrp->rx_db0_control->get_freq_range(fmin, fmax, fstep); 297 } else if (channel == 1) { 298 if (usrp->rx_db1_control) 299 usrp->rx_db1_control->get_freq_range(fmin, fmax, fstep); 289 if (usrp->rx_db0_control) { 290 fmin = usrp->rx_db0_control->freq_min(); 291 fmax = usrp->rx_db0_control->freq_max(); 292 fstep = 0; 293 } 294 } else if (channel == 1) { 295 if (usrp->rx_db1_control) { 296 fmin = usrp->rx_db1_control->freq_min(); 297 fmax = usrp->rx_db1_control->freq_max(); 298 fstep = 0; 299 } 300 300 } else { 301 301 return; ///\todo throw bad channel exception … … 307 307 DEBUG(3, USRP, "In RX Control set frequency channel: " << channel << ", frequency: " << f); 308 308 309 class db_base *db(NULL); 309 db_base_sptr db; 310 usrp_tune_result result; 310 311 311 312 omni_mutex_lock l(usrp->rx_control_access); … … 321 322 } 322 323 323 if (!db) { 324 DEBUG(1, USRP, "Attempt to set frequency for slot with no board."); 325 return; // No daughter board present 326 } 327 328 float fmin, fmax, fstep; 329 db->get_freq_range(fmin, fmax, fstep); 330 if ((f < fmin) || (f > fmax)) { 331 std::cerr << "Frequency setting not in range " << fmin << " < " << f << " < " << fmax << std::endl; 332 return; /// \todo throw exception 333 } 334 335 if (db->db_has_lo()) { 336 if (!lo_locked) { 337 float db_lo_freq_set = f + db_lo_offset; 338 if (db_lo_freq_set < fmin) 339 db_lo_freq_set = fmin; 340 else if (db_lo_freq_set > fmax) 341 db_lo_freq_set = fmax; 342 343 bool freq_set = db->set_db_freq(db_lo_freq_set, db_lo_freq); 344 if (freq_set) 345 DEBUG(3, USRP, "Set db lo to " << (long)db_lo_freq_set << ", Actual setting " << (float) db_lo_freq) 346 else 347 std::cerr << "Failed to set db lo to " << (float) db_lo_freq_set << std::endl; 348 } 349 } else 350 db_lo_freq = 0.0; 351 352 float ddc_freq = f - db_lo_freq; 353 if ((ddc_freq < 0e6) || (ddc_freq > 32e6)) { 354 std::cerr << "Frequency for DDC not in range 0 < " << ddc_freq << " < 32e6" << std::endl; 355 return; ///\todo throw an exception 356 } 357 358 usrp->usrp_rx->set_rx_freq(channel, ddc_freq); 359 DEBUG(3, USRP, "Setting ddc lo to " << (long)ddc_freq << " Actual frequency " << (long)usrp->usrp_rx->rx_freq(channel)) 360 324 if (!usrp->usrp_rx->tune(channel, db, f, &result)) { 325 DEBUG(3, USRP, "USRP RX set_frequency failed"); 326 return; // throw exception 327 } 328 329 DEBUG(3, USRP, "USRP RX tune_result:" << 330 " baseband_freq=" << result.baseband_freq << 331 " dxc_freq=" << result.dxc_freq << 332 " residual_freq=" << result.residual_freq << 333 " inverted=" << result.inverted); 361 334 } 362 335 … … 368 341 void USRP_RX_Control_i::start(CORBA::ULong channel) 369 342 { 370 371 343 omni_mutex_lock l(usrp->rx_control_access); 372 344
